• Title, Summary, Keyword: Flow-based network processor

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Multicore Flow Processor with Wire-Speed Flow Admission Control

  • Doo, Kyeong-Hwan;Yoon, Bin-Yeong;Lee, Bhum-Cheol;Lee, Soon-Seok;Han, Man Soo;Kim, Whan-Woo
    • ETRI Journal
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    • v.34 no.6
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    • pp.827-837
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    • 2012
  • We propose a flow admission control (FAC) for setting up a wire-speed connection for new flows based on their negotiated bandwidth. It also terminates a flow that does not have a packet transmitted within a certain period determined by the users. The FAC can be used to provide a reliable transmission of user datagram and transmission control protocol applications. If the period of flows can be set to a short time period, we can monitor active flows that carry a packet over networks during the flow period. Such powerful flow management can also be applied to security systems to detect a denial-of-service attack. We implement a network processor called a flow management network processor (FMNP), which is the second generation of the device that supports FAC. It has forty reduced instruction set computer core processors optimized for packet processing. It is fabricated in 65-nm CMOS technology and has a 40-Gbps process performance. We prove that a flow router equipped with an FMNP is better than legacy systems in terms of throughput and packet loss.

Design and Implementation of Xcent-Net

  • Park, Kyoung;Hahn, Jong-Seok;Sim, Won-Sae;Hahn, Woo-Jong
    • Journal of Electrical Engineering and information Science
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    • v.2 no.6
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    • pp.74-81
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    • 1997
  • Xcent-Net is a new system network designed to support a clustered SMP called SPAX(Scalable Parallel Architecture based on Xbar) that is being developed by ETRI. It is a duplicated hierarchical crossbar network to provide the connections among 16 clusters of 128 nodes. Xcent-Net is designed as a packet switched, virtual cut-through routed, point-to-point network. Variable length packets contain up to 64 bytes of data. The packets are transmitted via full duplexed, 32-bit wide channels using source synchronous transmission technique. Its plesiochronous clocking scheme eliminates the global clock distribution problem. Two level priority-based round-robin scheme is adopted to resolve the traffic congestion. Clear-to-send mechanism is used as a packet level flow control scheme. Most of functions are built in Xcent router, which is implemented as an ASIC. This paper describes the architecture and the functional features of Xcent-Net and discusses its implementation.

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Code Generation and Optimization for the Flow-based Network Processor based on LLVM

  • Lee, SangHee;Lee, Hokyoon;Kim, Seon Wook;Heo, Hwanjo;Park, Jongdae
    • Proceedings of the Korea Information Processing Society Conference
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    • pp.42-45
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    • 2012
  • A network processor (NP) is an application-specific instruction-set processor for fast and efficient packet processing. There are many issues in compiler's code generation and optimization due to NP's hardware constraints and special hardware support. In this paper, we describe in detail how to resolve the issues. Our compiler was developed on LLVM 3.0 and the NP target was our in-house network processor which consists of 32 64-bit RISC processors and supports multi-context with special hardware structures. Our compiler incurs only 9.36% code size overhead over hand-written code while satisfying QoS, and the generated code was tested on a real packet processing hardware, called S20 for code verification and performance evaluation.

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Implementation of 40 Gb/s Network Processor of Wire-Speed Flow Management (40 Gb/s 실시간 플로우 관리 네트워크 프로세서 구현)

  • Doo, Kyeong-Hwan;Lee, Bhum-Cheol;Kim, Whan-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37B no.9
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    • pp.814-821
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    • 2012
  • We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.

Development of the Contingency Analysis Program of Korean Energy Management System (한국형 에너지 관리시스템용 상정고장 해석프로그램 개발)

  • Cho, Yoon-Sung;Yun, Sang-Yun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.2
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    • pp.232-241
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    • 2010
  • This paper describes the development of robust contingency analysis program for Korean Energy Management System. The important function of contingency analysis is to determine the bus/branch model for contingency, and to calculate the state of the power network based on the network model and topology output. In the proposed method, the bus/branch models for contingencies are determined exactly using a fast linked-list method based on the application common model database. To calculate the state of the power system included contingency, the full-decoupled powerflow approach, the partial powerflow method for contingencies and the proposed contingency screening algorithm are also used to contingency analysis. To verify the performance of the developed processor, we performed a file-based test using several structured input data and online test using the database which resides on memory. The results of these comprehensive tests showed that the developed processors can accurately calculate the power system contingency state from online data and can be applied to Korea Power Exchange system.

A Study on the Flow Control Based Estimated Receiving Capacity on the Video Conference System (화상회의 시스템에서 수신능력 예측을 이용한 흐름제어에 관한 연구)

  • 김상진;남지승
    • Journal of Korea Multimedia Society
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    • v.6 no.3
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    • pp.488-495
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    • 2003
  • With the development of networks, multimedia communication has expanded its application field. From the remote control for household electric appliances to medicine, games, video conferencing and multimedia chatting, multimedia communication is being used in all parts of our lives. This multimedia communication requires the transmission of a lot of data at high speed. But if the transmission rate of the communication network exceeds the processing speed of being used in the high speed network environment, a bottleneck occurs in each node and deteriorates the performance of the network. This is the main reason for the slow speed of data transmission and packet loss. In this paper, considering the client's processing performance, reception performance was predicted and the way of flow control was shown. The computing performance of relevant Processor and its performance was estimated through the actual implementation.

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Delay Guaranteed Fair Queueing (DGFQ) in Multimedia Wireless Packet Networks (멀티미디어 무선 패킷망에서 지연시간을 보장하는 공정큐잉)

  • Yang, Hyunho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.5
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    • pp.916-924
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    • 2003
  • Fair queueing has been an important issue in the multimedia networks where resources are shared among nodes both wired and wireless. In most fair queuing algorithms, based on the generalized processor sharing(GPS), emphasizes fairness guarantee while overlooking bounded delay guarantee which is critical to support multimedia services in the networks. In this paper, we propose a new fair queueing scheme, delay guaranteed fair queueing (DGFQ), which guaranteeing bounded delay of flows according to their individual delay requirements for multimedia services in the wireless packet networks.

Optimal Interface Design between Short-Range Air Defense Missile System and Dissimilar Combat Systems (단거리 대공방어유도탄체계와 이기종 함정 전투체계간 최적의 연동 설계 기법)

  • Park, Hyeon-Woo
    • Journal of the Korea Institute of Military Science and Technology
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    • v.18 no.3
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    • pp.260-266
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    • 2015
  • The warship is run based on the combat system which shares tactical information collected by target detection systems and navigation devices across a network, and conducts the command and control of weapons from target detection to kill assessment. The short-range air defense missile system defends a warship from anti-ship missiles, aircraft, helicopter and other threats in order to contribute to the survival of a warship and the success of missions. The short-range air defense missile system is applied to a various combat systems. In this paper, we have proposed the interface design between the short-range air defense missile and dissimilar combat systems. To employ the short-range air defense missile at dissimilar combat systems, each system is driven by independent processor, and the tasks which are performed by each system are assigned. The information created by them is exchanged through the interface, and the flow of messages is designed.

A Study on a Bandwidth Guarantee Method of Subscriber-based DiffServ in Access Networks (액세스 망에서의 DiffServ 기반 가입자 대역 보장 방법 연구)

  • Park, Hea-Sook;Kim, Hae-Sook;Youn, Cheong
    • The KIPS Transactions:PartC
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    • v.12C no.5
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    • pp.709-716
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    • 2005
  • QoS is an important requirement of the FTTH (Fiber To The Home) subscriber in access network using E-PON (Ethernet Passive Optical Network). In this research, we describe the structure of the access network and propose a bandwidth guarantee scheme for subscriber and service according to the requirements of the subscriber, service and system. This scheme uses two kinds of the classification table, which are called 'service classification table' and 'subscriber classification table.' Using the classification table, we can identify the flow of the subscriber and service. Also, we compute the number of hash table entry to minimize the loss ratio of flows using the M/G/k/k queueing model. Finally, we apply the DRR scheduling through virtual queueing per subscriber instead of the aggregated class.

Design and Implementation of a Hardware-based Transmission/Reception Accelerator for a Hybrid TCP/IP Offload Engine (하이브리드 TCP/IP Offload Engine을 위한 하드웨어 기반 송수신 가속기의 설계 및 구현)

  • Jang, Han-Kook;Chung, Sang-Hwa;Yoo, Dae-Hyun
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.9
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    • pp.459-466
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    • 2007
  • TCP/IP processing imposes a heavy load on the host CPU when it is processed by the host CPU on a very high-speed network. Recently the TCP/IP Offload Engine (TOE), which processes TCP/IP on a network adapter instead of the host CPU, has become an attractive solution to reduce the load in the host CPU. There have been two approaches to implement TOE. One is the software TOE in which TCP/IP is processed by an embedded processor and the other is the hardware TOE in which TCP/IP is processed by a dedicated ASIC. The software TOE has poor performance and the hardware TOE is neither flexible nor expandable enough to add new features. In this paper we designed and implemented a hybrid TOE architecture, in which TCP/IP is processed by cooperation of hardware and software, based on an FPGA that has two embedded processor cores. The hybrid TOE can have high performance by processing time-critical operations such as making and processing data packets in hardware. The software based on the embedded Linux performs operations that are not time-critical such as connection establishment, flow control and congestions, thus the hybrid TOE can have enough flexibility and expandability. To improve the performance of the hybrid TOE, we developed a hardware-based transmission/reception accelerator that processes important operations such as creating data packets. In the experiments the hybrid TOE shows the minimum latency of about $19{\mu}s$. The CPU utilization of the hybrid TOE is below 6 % and the maximum bandwidth of the hybrid TOE is about 675 Mbps.