• Title, Summary, Keyword: Hardware

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Automatic Hardware/Software Interface Generation for Embedded System

  • Son, Choon-Ho;Yun, Jeong-Han;Kang, Hyun-Goo;Han, Tai-Sook
    • Journal of Information Processing Systems
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    • v.2 no.3
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    • pp.137-142
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    • 2006
  • A large portion of the embedded system development process involves the integration of hardware and software. Unfortunately, communication across the hardware/software boundary is tedious and error-prone to create. This paper presents an automatic hardware/software interface generation system. As the front-end of hardware/software co-design frameworks, a system designer defines XML specifications for hardware functions. Our system generates hardware/software interfaces including Device Driver, Driver API, and Device Controller from these specifications. Embedded software designers can easily use hardware just like system libraries. Our system reduces the mistakes and errors that can be occurred when a software programmer directly connects software to hardware, and supports balancing labors between hardware developers and software programmers. Moreover, this system can be used as the back-end for a hardware/software co-design framework.

Hardware Implementation of Genetic Algorithm for Evolvable Hardware (진화하드웨어 구현을 위한 유전알고리즘 설계)

  • Dong, Sung-Soo;Lee, Chong-Ho
    • 전자공학회논문지 IE
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    • v.45 no.4
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    • pp.27-32
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    • 2008
  • This paper presents the implementation of simple genetic algorithm using hardware description language for evolvable hardware embedded system. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results for several fitness functions.

Virtual Prototyping of Area-Based Fast Image Stitching Algorithm

  • Mudragada, Lakshmi Kalyani;Lee, Kye-Shin;Kim, Byung-Gyu
    • Journal of Multimedia Information System
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    • v.6 no.1
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    • pp.7-14
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    • 2019
  • This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

Behavior Evolution of Autonomous Mobile Robot(AMR) using Genetic Programming Based on Evolvable Hardware

  • Sim, Kwee-Bo;Lee, Dong-Wook;Zhang, Byoung-Tak
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.2 no.1
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    • pp.20-25
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    • 2002
  • This paper presents a genetic programming based evolutionary strategy for on-line adaptive learnable evolvable hardware. Genetic programming can be useful control method for evolvable hardware for its unique tree structured chromosome. However it is difficult to represent tree structured chromosome on hardware, and it is difficult to use crossover operator on hardware. Therefore, genetic programming is not so popular as genetic algorithms in evolvable hardware community in spite of its possible strength. We propose a chromosome representation methods and a hardware implementation method that can be helpful to this situation. Our method uses context switchable identical block structure to implement genetic tree on evolvable hardware. We composed an evolutionary strategy for evolvable hardware by combining proposed method with other's striking research results. Proposed method is applied to the autonomous mobile robots cooperation problem to verify its usefulness.

Design of Evolvable Hardware for Behavior Evolution of Autonomous Mobile Robots (자율이동로봇의 행동진화를 위한 진화하드웨어 설계)

  • 이동욱;반창봉;전호병;심귀보
    • 제어로봇시스템학회:학술대회논문집
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    • pp.254-254
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    • 2000
  • This paper presents a genetic programming based evolutionary strategy for on-line adaptive learnable evolvable hardware. genetic programming can be useful control method for evolvable hardware for its unique tree structured chromosome. However it is difficult to represent tree structured chromosome on hardware, and it is difficult to use crossover operator on hardware. Therefore, genetic programming is not so popular as genetic algorithms in evolvable hardware community in spite of its possible strength. We propose a chromosome representation methods and a hardware implementation method that can be helpful to this situation. Our method uses context switchable identical block structure to implement genetic tree on evolvable hardware. We composed an evolutionary strategy (or evolvable hardware by combining proposed method with other's striking research results. Proposed method is applied to the autonomous mobile robots cooperation problem to verify its usefulness.

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Partioning for hardwae-software codesign (하드웨어-소프트웨어 통합 설계를 위한 분할)

  • 윤경로;박동하;신현철
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.261-268
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    • 1996
  • Hardware-software codesign becomes improtant to effectively sagisfy perfomrance goals, because designers can trade-off in the way hardware and software components work teogether to exhibit a specified behavior. In this paper, a hardware-software pratitioning algorithm is presetned, in which the system behavioral description containing a mixture of hardware and software components is partitioned into hardware part and software part. The partitioning algorithm tries to minimize the given cost function under constraints on hardware resources or latency. Recursive moving of operations between the hardware and software parts is used to find a near optimum partition and the list scheduling approach is used to estimate the hardware area and latency. Since memory may take substantial protion of the hardware part, memory cost is included in sthe hardware cost. Experimental resutls show that our algorithm is effective.

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A Methodology for Estimating Optimum Hardware Capacity E-learning System Development (E-러닝시스템 구축 프로젝트의 적정 하드웨어 산정방법론 연구)

  • Jung, Ji-Young;Baek, Dong-Hyun
    • Journal of the Society of Korea Industrial and Systems Engineering
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    • v.34 no.3
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    • pp.49-56
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    • 2011
  • Estimating optimum hardware capacity of an e-learning system is very important process to grasp reasonable size of designing technique architecture and budget during step of ISP(information strategic planning) and development. It hugely influences cost and quality of the whole project. While investment on information system hardware has been continuously increased, there was no certified hardware capacity estimating method in e-learning system development. A guideline for hardware sizing of information systems was established by Telecommunication Technology Association in 2008. However, the guideline is not appropriate for estimating optimum hardware capacity of an e-learning system because it was designed to provide general standards for estimating hardware capacity of various types of projects. The purpose of this paper is to provide a methodology for estimating optimum hardware capacity in e-learning system development. To develop the methodology, this study, first of all, analyzes two e-learning development projects, in which the guideline was applied to estimate optimum hardware capacity. Then, this study finds out several key factors influencing on hardware capacity. Finally, this study suggests a methodology for estimating optimum hardware capacity of an e-learning system, in which weights for the factors are determined through AHP analysis.

Hardware Implementation of Genetic Algorithm and Its Analysis (유전알고리즘의 하드웨어 구현 및 실험과 분석)

  • Dong, Sung-Soo;Lee, Chong-Ho
    • 전자공학회논문지 IE
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    • v.46 no.2
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    • pp.7-10
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    • 2009
  • This paper presents the implementation of libraries of hardware modules for genetic algorithm using VHDL. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results and analysis for several fitness functions. It can be seen that our design works well for the three examples.

ISO 26262 의 하드웨어 ASIL 정량적 평가 절차

  • Kim, Gi-Yeong;Jang, Jung-Sun
    • Proceedings of the Korean Reliability Society Conference
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    • pp.271-279
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    • 2011
  • Automotive safety integrity level of hardware components can be achieved by satisfying quantitative and qualitative requirements. Based on ASIL, quantitative requirements are composed of hardware architectural metrics and evaluation of safety goal violations due to random hardware failures in ISO 26262. In this paper, the types of hardware failures will be defined and classified. Based on various metrics related with hardware failures, design essentials to achieve hardware safety integrity will be studied specifically. Issues associated with hardware development and assessment process are presented briefly.

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A Study on the EHW Chip Architecture (EHW 칩 아키텍쳐에 관한 연구)

  • Kim, Jong-O;Kim, Duck-Soo;Lee, Won-Seok
    • Proceedings of the IEEK Conference
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    • pp.1187-1188
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    • 2008
  • An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

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