• Title, Summary, Keyword: Hardware design

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Automatic Hardware/Software Interface Generation for Embedded System

  • Son, Choon-Ho;Yun, Jeong-Han;Kang, Hyun-Goo;Han, Tai-Sook
    • Journal of Information Processing Systems
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    • v.2 no.3
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    • pp.137-142
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    • 2006
  • A large portion of the embedded system development process involves the integration of hardware and software. Unfortunately, communication across the hardware/software boundary is tedious and error-prone to create. This paper presents an automatic hardware/software interface generation system. As the front-end of hardware/software co-design frameworks, a system designer defines XML specifications for hardware functions. Our system generates hardware/software interfaces including Device Driver, Driver API, and Device Controller from these specifications. Embedded software designers can easily use hardware just like system libraries. Our system reduces the mistakes and errors that can be occurred when a software programmer directly connects software to hardware, and supports balancing labors between hardware developers and software programmers. Moreover, this system can be used as the back-end for a hardware/software co-design framework.

A design of PCI-based reconfigurable verification environment for IP design (IP 검증을 위한 PCI 기반 리프로그램머블 설계 기능 에뮬레이션 환경 구현)

  • 최광재;조용권;이문기
    • Proceedings of the IEEK Conference
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    • pp.65-68
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    • 2002
  • The verification of software part and HW/SW interface suffer from the absence of the hardware platform at the end of partitioning and coding phase in design cycle. In this paper we present the design of easy verification for hardware design. Hardware and software engineer can verify their software program and hardware design for a chip that is emulated in proposed verification environment. Besides, designer can easily design the DEMO system.

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Virtual Prototyping of Area-Based Fast Image Stitching Algorithm

  • Mudragada, Lakshmi Kalyani;Lee, Kye-Shin;Kim, Byung-Gyu
    • Journal of Multimedia Information System
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    • v.6 no.1
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    • pp.7-14
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    • 2019
  • This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

Hardware design system with the voice communication

  • Honda, Akihito;Araki, Hideo;Harashima, Katsumi;Kutuwa, Toshiro
    • Proceedings of the IEEK Conference
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    • pp.208-211
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    • 2002
  • At present there is no hardware design system by using the voice. We try to use the voice communication to the hardware design and to communication with the computer. This time, we make au application that introduces voice communication and we execute small-scale circuit description.

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Introduction to Evolvable Hardware Design

  • Kim Jong O;Kim Duk Soo;Kim Young Gun
    • Proceedings of the IEEK Conference
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    • pp.509-513
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    • 2004
  • An area of research called evolvable hardware (EHW) has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. This paper gives an introduction to the field. It continues by including classifying the EHW and the applications of the area.

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A Study on Embodiment of Evolving Cellular Automata Neural Systems using Evolvable Hardware

  • Sim, Kwee-Bo;Ban, Chang-Bong
    • Journal of the Korean Institute of Intelligent Systems
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    • v.11 no.8
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    • pp.746-753
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    • 2001
  • In this paper, we review the basic concept of Evolvable Hardware first. And we examine genetic algorithm processor and hardware reconfiguration method and implementation. By considering complexity and performance of hardware at the same time, we design genetic algorithm processor using modularization and parallel processing method. And we design frame that has connection structure and logic block on FPGA, and embody reconfigurable hardware that do so that this frame may be reconstructed by RAM. Also we implemented ECANS that information processing system such as living creatures'brain using this hardware reconfiguration method. And we apply ECANS which is implemented using the concept of Evolvable Hardware to time-series prediction problem in order to verify the effectiveness.

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Gradient Magnitude Hardware Architecture based on Hardware Folding Design Method for Low Power Image Feature Extraction Hardware Design (저전력 영상 특징 추출 하드웨어 설계를 위한 하드웨어 폴딩 기법 기반 그라디언트 매그니튜드 연산기 구조)

  • Kim, WooSuk;Lee, Juseong;An, Ho-Myoung
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.10 no.2
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    • pp.141-146
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    • 2017
  • In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

An Effective Evolvable Hardware Design using Module Evolution (모듈진화를 이용한 효율적인 진화 하드웨어 설계)

  • 황금성;조성배
    • Journal of KIISE:Software and Applications
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    • v.31 no.10
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    • pp.1364-1373
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    • 2004
  • Recently Evolvable Hardware (EHW) is widely studied to design effective hardware circuits that can reconfigure themselves according to the environment. However, it is still difficult to apply for complicated circuits because the search space increases exponentially as the complexity of hardware increases. To remedy this problem, this paper proposes a method to evolve complex hardware with a modular approach. The comparative experiments of some digital circuits with the conventional evolutionary approach indicate that the proposed method yields from 50 times to 1,000 times faster evolution and more optimized hardware.

A VLSI Design of IDEA Cipher Algorithm Based On a Single Iterative Round Method (단일 라운드 프로세스 방식의 IDEA 암호 알고리즘의 하드웨어 설계)

  • 최영민;권용진
    • Proceedings of the IEEK Conference
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    • pp.144-147
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    • 2000
  • Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.

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Analysis of Verification Methodologies Based on a SoC Platform Design

  • Lee, Je-Hoon;Kim, Sang-Choon
    • International Journal of Contents
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    • v.7 no.1
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    • pp.23-28
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    • 2011
  • In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.