• 제목, 요약, 키워드: High-performance Router

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A Study on the Performance Analysis of a High-Speed ATM Router (고속 ATM 라우터의 성능 분석에 관한 연구)

  • 조성국
    • Journal of the Korea Society of Computer and Information
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    • v.6 no.1
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    • pp.74-81
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    • 2001
  • In this paper. the architecture of a high-speed ATM router using ATM switch is studied and the performance of the high-speed ATM router is analyzed through simulation. The high-speed ATM router using ATM switch is able to reduce the load of router and the processing time of a packet in the router. The size of router buffers has been studied through simulation processes for the analysis of performance capacity in due course of making changes in routing time(RT), which is the performance capacity parameters of high-speed ATM routers, flow table size(FS), flow live time(FT) and input circuit efficiencies. The result of this study can be used as the source material for analyzing the suitability of equipment in upgrading networks and applying high-speed ATM routers by using ATM switches.

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Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

  • Deivakani, M.;Shanthi, D.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.6
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    • pp.736-744
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    • 2016
  • Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

FDVRRP: Router implementation for fast detection and high availability in network failure cases

  • Lee, Changsik;Kim, Suncheul;Ryu, Hoyong
    • ETRI Journal
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    • v.41 no.4
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    • pp.473-482
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    • 2019
  • High availability and reliability have been considered promising requirements for the support of seamless network services such as real-time video streaming, gaming, and virtual and augmented reality. Increased availability can be achieved within a local area network with the use of the virtual router redundancy protocol that utilizes backup routers to provide a backup path in the case of a master router failure. However, the network may still lose a large number of packets during a failover owing to a late failure detections and lazy responses. To achieve an efficient failover, we propose the implementation of fast detection with virtual router redundancy protocol (FDVRRP) in which the backup router quickly detects a link failure and immediately serves as the master router. We implemented the FDVRRP using open neutralized network operating system (OpenN2OS), which is an open-source-based network operating system. Based on the failover performance test of OpenN2OS, we verified that the FDVRRP exhibits a very fast failure detection and a failover with low-overhead packets.

A Study on the Router Bottle Neck for Campus Network (캠퍼스 네트워크에서의 라우터의 병목 현상에 관한 연구)

  • 고봉구;안동언정성종
    • Proceedings of the IEEK Conference
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    • pp.253-256
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    • 1998
  • In this paper, we discuss the CPU Utilization and bottle neck of the router on campus network. Generally, high CPU utilization does not only makes slow network speed but also frequently network disconnection. The above characteristic is based on the network with one router. In order to solve this problem, we reconstruct network configuration with two routers. Our result shows that CPU utilization of network topology with two router have good performance compared to that with one.

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Study on High Speed Routers(I)-Labeling Algorithms for STC104 (고속라우터에 대한 고찰(I)-STC104의 레이블링 알고리즘)

  • Lee, Hyo-Jong
    • The KIPS Transactions:PartA
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    • v.8A no.2
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    • pp.147-156
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    • 2001
  • A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

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An Implementation of High-performance Router Platform Supporting IPv6 that can High-speed Wired/wireless Interface and QoS (IPv6를 지원하는 초고속 유/무선 인터페이스와 QoS제공 가능한 고성능 라우터 플랫폼 개발)

  • Ryoo, Kwang-Seok;Seo, In-Ho;Shin, Jae-Heung
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.66 no.4
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    • pp.229-235
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    • 2017
  • Until now, a study on a ubiquitous sensor network has been mainly concentrated in the areas of sensor nodes, and as a results, technologies related with sensor node were greatly developed. Despite of many achievements on research and development for a sensor node, a ubiquitous sensor network may failed to establish the actual service environment because variety of restrictions. In order to provide a actual service using a ubiquitous sensor networks applied to many results on research and development for a sensor nodes, a study on a wired/wireless composite router must be carried out. However a study on a wired/wireless composite router is relatively very slow compared with the sensor node. In this study, developed a high-performance router platform supporting IPv6 that can provide high-speed wired/wireless interface and QoS, and it can provide the multimedia service Interlocking the wireless sensor network and the Internet network. To analysis a given network environment and to develop the appropriate hardware and software in accordance with this requirement.

High Performance 32-bit Embedded AES for Wireless Network Router Applications (무선 네트웤 라우터응용을 위한 고성능32비트 내장AES)

  • Lin, Deng;You, Young-Gap
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.11
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    • pp.97-104
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    • 2010
  • This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.

Simulation Analysis for Verifying an Implementation Method of Higher-performed Packet Routing

  • Park, Jaewoo;Lim, Seong-Yong;Lee, Kyou-Ho
    • Proceedings of the Korea Society for Simulation Conference
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    • pp.440-443
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    • 2001
  • As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

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High Performance IP Address Lookup Using GPU

  • Kim, Junghwan;Kim, Jinsoo
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.5
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    • pp.49-56
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    • 2016
  • Increasing Internet traffic and forwarding table size need high performance IP address lookup engine which is a crucial function of routers. For finding the longest matching prefix, trie-based or its variant schemes have been widely researched in software-based IP lookup. As a software router, we enhance the IP address lookup engine using GPU which is a device widely used in high performance applications. We propose a data structure for multibit trie to exploit GPU hardware efficiently. Also, we devise a novel scheme that the root subtrie is loaded on Shared Memory which is specialized for fast access in GPU. Since the root subtrie is accessed on every IP address lookup, its fast access improves the lookup performance. By means of the performance evaluation, our implemented GPU-based lookup engine shows 17~23 times better performance than CPU-based engine. Also, the fast access technique for the root subtrie gives 10% more improvement.

An Empirical Study on a Network Processor for a MPLS Router's Design and Implementation (MPLS 라우터 설계와 구현에서 네트워크 프로세서 사용의 경험적 고찰)

  • Kim, Eun-Ah;Chun, Woo-Jik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.4B
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    • pp.339-350
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    • 2003
  • The demands of network users emphasize the improvement and guarantee of service quality as well as the increment of bandwidth. As a result, high performance and additional new functions are important features to build network equipments, especially and edge router. For this structure, network processors with high performance and flexibility are considered as a main part of a packet forwarding module. In this paper, we design and edge MPLS router with a network processor, which supports high performance and multi-functionalities and examine its advantage and limitation.