• Title, Summary, Keyword: High-performance video processors

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Design and Implementation MoIP Wall-pad platform using ARM11 (ARM11 을 이용한 MoIP 월패드 플랫폼 구현)

  • Jung, Yong-Kuk;Kim, Dae-Sung;Heo, Kwang-Seon;Kweon, Min-Su;Choi, Young-Gyu
    • Proceedings of the Korea Information Processing Society Conference
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    • pp.46-49
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    • 2011
  • This paper is to implement MoIP platform to send and receive video and audio at the same time by using high-performance Dual Core Processor. Even if Wall-Pad key component of a home network system is released by using embedded processors, it's lacking of performance in terms of multimedia processing and feature of video telephony through which video and voice are exchanged simultaneously. The main reason could be that embedded processors currently being used do not provide enough performance to support both MoIP call features and various home network features simultaneously. In order to solve these problems, Dual processor could be used, but in the other hands it brings another disadvantage of high cost. Therefore, this study is to solve the home automation features and video telephony features by using Dual Core Processor based on ARM 11 Processor and implement the MoIP Wall-Pad which can reduce the board design costs and component costs, and improve performance. The platform designed and implemented in this paper verified performance of MoIP to exchange the video and voice at the same time under the situation of Ethernet network.

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Simulation of YUV-Aware Instructions for High-Performance, Low-Power Embedded Video Processors (고성능, 저전력 임베디드 비디오 프로세서를 위한 YUV 인식 명령어의 시뮬레이션)

  • Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.5
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    • pp.252-259
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    • 2007
  • With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

Implementation of Energy-Efficient Multimedia Embedded System using PXA270 processor (PXA270 프로세서를 사용한 저전력 멀티미디어 임베디드 시스템의 구현)

  • Kim, Sang-Duck;Lee, Hoo-Sung;Park, Seong-Su
    • Proceedings of the IEEK Conference
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    • pp.945-948
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    • 2005
  • In wireless and handheld platforms area, performance, power and cost are key metrics for product success. This is driving increasing levels of on-chip integration in state-of-the-art application processors. The purpose of this project is to optimize and design the energy-efficient embedded system that properly displays video and audio in real time. The requirements are for the media player to be capable of decoding real-time streaming video and audio with the least possible energy consumption for a variety of different clips at different resolutions. We implemented this Linux based multimedia player on Intel's PXA27x platform.

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Implementation of SIMD-based Many-Core Processor for Efficient Image Data Processing (효율적인 영상데이터 처리를 위한 SIMD기반 매니코어 프로세서 구현)

  • Choi, Byong-Kook;Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.1
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    • pp.1-9
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    • 2011
  • Recently, as mobile multimedia devices are used more and more, the needs for high-performance and low-energy multimedia processors are increasing. Application-specific integrated circuits (ASIC) can meet the needed high performance for mobile multimedia, but they provide limited, if any, generality needed for various application requirements. DSP based systems can used for various types of applications due to their generality, but they require higher cost and energy consumption as well as less performance than ASICs. To solve this problem, this paper proposes a single instruction multiple data (SIMD) based many-core processor which supports high-performance and low-power image data processing while keeping generality. The proposed SIMD based many-core processor composed of 16 processing elements (PEs) exploits large data parallelism inherent in image data processing. Experimental results indicate that the proposed SIMD-based many-core processor higher performance (22 times better), energy efficiency (7 times better), and area efficiency (3 times better) than conversional commercial high-performance processors.

Simulation of Wood Crib Burning Behaviors by Using FDS (FDS를 이용한 소화모형 화재거동의 시뮬레이션)

  • Kwon, Seong-Pil;Yoon, Hun-Ju;Kim, Hyeong-Gweon;Ra, Yong-Woon;SaKong, Seong-Ho;Shin, Dong-Il
    • Proceedings of the Korea Institute of Fire Science and Engineering Conference
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    • pp.76-79
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    • 2008
  • In this work wood crib burning behaviors have been simulated by using the FDS(Fire Dynamic Simulator) program. Wood cribs are regularly stacked arrays of wood sticks, and available for the performance rating of fire-extinguishers. On the basis of an angle iron supporter 26 layers of wood sticks have been stacked up. Each layer consists of 5 or 6 wood sticks which are placed in parallel, with a constant distance, and in alternating rows. They are laid between the horizontally adjacent sticks at the before last layer. The wood crib is ignited instantaneously by an amount of burning gasoline below. A comprehensive simulation of such a practical sophisticated combustion is still too difficult to realize with any currently available computer, although the performance of modern processors is getting better everyday. We could carry it out here through parallel computing on the HPC(High Performance Computing) cluster as the feasible alternative. At last the validation has been executed by means of temperature distribution data measured by the thermal video camera.

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Performance Study of Multicore Digital Signal Processor Architectures (멀티코어 디지털 신호처리 프로세서의 성능 연구)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.4
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    • pp.171-177
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    • 2013
  • Due to the demand for high speed 3D graphic rendering, video file format conversion, compression, encryption and decryption technologies, the importance of digital signal processor system is growing rapidly. In order to satisfy the real-time constraints, high performance digital signal processor is required. Therefore, as in general purpose computer systems, digital signal processor should be designed as multicore architecture as well. Using UTDSP benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2 to 16-core digital signal processor architectures with the cores from simple RISC to in-order and out-of-order superscalar processors for the various window sizes, extensively.

Simulation Analysis for Verifying an Implementation Method of Higher-performed Packet Routing

  • Park, Jaewoo;Lim, Seong-Yong;Lee, Kyou-Ho
    • Proceedings of the Korea Society for Simulation Conference
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    • pp.440-443
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    • 2001
  • As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

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Implementing Efficient Camera ISP Filters on GPGPUs Using OpenCL (GPGPU 기반의 효율적인 카메라 ISP 구현)

  • Park, Jongtae;Facchini, Beron;Hong, Jingun;Burgstaller, Bernd
    • Proceedings of the Korea Information Processing Society Conference
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    • pp.1784-1787
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    • 2010
  • General Purpose Graphic Processing Unit (GPGPU) computing is a technique that utilizes the high-performance many-core processors of high-end graphic cards for general-purpose computations such as 3D graphics, video/image processing, computer vision, scientific computing, HPC and many more. GPGPUs offer a vast amount of raw computing power, but programming is extremely challenging because of hardware idiosyncrasies. The open computing language (OpenCL) has been proposed as a vendor-independent GPGPU programming interface. OpenCL is very close to the hardware and thus does little to increase GPGPU programmability. In this paper we present how a set of digital camera image signal processing (ISP) filters can be realized efficiently on GPGPUs using OpenCL. Although we found ISP filters to be memory-bound computations, our GPGPU implementations achieve speedups of up to a factor of 64.8 over their sequential counterparts. On GPGPUs, our proposed optimizations achieved speedups between 145% and 275% over their baseline GPGPU implementations. Our experiments have been conducted on a Geforce GTX 275; because of OpenCL we expect our optimizations to be applicable to other architectures as well.

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Implementation of the Integrated Navigation Parameter Extraction from the Aerial Image Sequence Using TMS320C80 MVP (TMS320C80 MVP 상에서의 연속항공영상으리 이용한 통합 항법 변수 추출 시스템 구현)

  • Sin, Sang-Yun;Park, In-Jun;Lee, Yeong-Sam;Lee, Min-Gyu;Kim, Gwan-Seok;Jeong, Dong-Uk;Kim, In-Cheol;Park, Rae-Hong;Lee, Sang-Uk
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.39 no.3
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    • pp.49-57
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    • 2002
  • In this paper, we deal with a real time implementation of the integrated image-based navigation parameter extraction system using the TMS320C80 MVP(multimedia video processor). Our system consists of relative position estimation and absolute position compensation, which is further divided into high-resolution aerial image matching, DEM(Digital elevation model) matching, and IRS (Indian remote sensing) satellite image matching. Those algorithms are implemented in real time using the MVP. To achieve a real-time operation, an attempt is made to partition the aerial image and process the partitioned images in parallel using the four parallel processors in the MVP. We also examine the performance of the implemented integrated system in terms of the estimation accuracy, confirming a proper operation of the our system.

Selective B Slice Skip Decoding for Complexity Scalable H.264/AVC Video Decoder (H.264/AVC 복호화기의 복잡도 감소를 위한 선택적 B 슬라이스 복호화 스킵 방법)

  • Lee, Ho-Young;Kim, Jae-Hwan;Jeon, Byeung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.48 no.3
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    • pp.79-89
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    • 2011
  • Recent development of embedded processors makes it possible to play back video contents in real-time on portable devices. Because of their limited battery capacity and low computational performance, however, portable devices still have significant problems in real-time decoding of high quality or high resolution compressed video. Although previous approaches are successful in achieving complexity-scalable decoder by controlling computational complexity of decoding elements, they cause significant objective quality loss coming from mismatch between encoder and decoder. In this paper, we propose a selective B slice skip-decoding method to implement a low complexity video decoder. The proposed method performs selective skip decoding process of B slice which satisfies the proposed conditions. The skipped slices are reconstructed by simple reconstruction method utilizing adjacent reconstructed pictures. Experimental result shows that proposed method not only reduces computational complexity but also maintains subjective visual quality.