• Title, Summary, Keyword: LDPC 복호기

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An analysis of Optimal Design Conditions of Multi-mode LDPC Decoder for IEEE 802.11n WLAN System (IEEE 802.11n WLAN용 다중모드 LPDC 복호기의 최적 설계조건 분석)

  • Park, Hae-Won;Na, Young-Heon;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.2
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    • pp.432-438
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    • 2011
  • This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

An analysis of Multi-mode LDPC Decoder Performance for IEEE 802.11n WLAN (IEEE 802.11n WLAN용 Multi-mode LDPC 복호기의 성능 분석)

  • Park, Hae-Won;Na, Young-Heon;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.80-83
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    • 2010
  • This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

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Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory Relocation (연산기와 메모리 재사용을 이용한 효율적인 DVB-S2 규격의 LDPC 복호기 구조)

  • Park Jae-Geun;Lee Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9
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    • pp.31-37
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    • 2006
  • Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

A Study on High Speed LDPC Decoder Based on HSS (HSS기반의 고속 LDPC 복호기 연구)

  • Jung, Ji Won
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.5 no.3
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    • pp.164-168
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    • 2012
  • LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies Horizontal Shuffle Scheduling (HSS) algorithm. In the result, number of iteration is half than conventional algorithm without performance degradation. Finally, this paper present design methodology of high-speed LDPC decoder and confirmed its throughput is up to about 600Mbps.

A Study on Turbo Equalization for MIMO Systems Based on LDPC Codes (MIMO 시스템에서 LDPC 부호 기반의 터보등화 방식 연구)

  • Baek, Chang-Uk;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.5
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    • pp.504-511
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    • 2016
  • In this paper, MIMO system based on turbo equalization techniques which LDPC codes were outer code and space time trellis codes (STTC) were employed as an inner code are studied. LDPC decoder and STTC decoder are connected through the interleaving and de-interleaving that updates each other's information repeatedly. In conventional turbo equalization of MIMO system, BCJR decoder which decodes STTC coded bits required two-bit wise decoding processing. Therefore duo-binary turbo codes are optimal for MIMO system combined with STTC codes. However a LDPC decoder requires bit unit processing, because LDPC codes can't be applied to these system. Therefore this paper proposed turbo equalization for MIMO system based on LDPC codes combined with STTC codes. By the simulation results, we confirmed performance of proposed turbo equalization model was improved about 0.6dB than that of conventional LDPC codes.

Equivalence of Binary Perturbation and Afterburner LDPC Decoder (이진 섭동과 에프터버너 LDPC 복호기의 동등성)

  • Lee, Hyunjae;Baek, Eun Chong;Kim, Sang-Hyo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.12
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    • pp.1742-1744
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    • 2016
  • In this letter, we prove equivalence of the Binary perturbation and Afterburner LDPC decoder that are proposed for improving the decoding performance in short length LDPC codes.

Pipeline-Aware QC-IRA-LDPC Code and Efficient Decoder Architecture (Pipeline-Aware QC-IRA-LDPC 부호 및 효율적인 복호기 구조)

  • Ajaz, Sabooh;Lee, Hanho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.10
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    • pp.72-79
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    • 2014
  • This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

Low-Complexity and High-Speed Multi-Size Circular Shifter With Benes Network Control Signal Optimization for WiMAX QC-LDPC Decoder (Benes 네트워크 제어 신호 최적화를 이용한 WiMAX QC-LDPC 복호기용 저면적/고속 Multi-Size Circular Shifter)

  • Kang, Hyeong-Ju
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.10
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    • pp.2367-2372
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    • 2015
  • One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

High-Throughput QC-LDPC Decoder Architecture for Multi-Gigabit WPAN Systems (멀티-기가비트 WPAN 시스템을 위한 고속 QC-LDPC 복호기 구조)

  • Lee, Hanho;Ajaz, Sabooh
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.104-113
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    • 2013
  • A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

Iterative Detection and Decoding of LDPC-Coded Multiuser Uplink Massive-MIMO Systems (LDPC 부호화된 멀티유저 상향링크 Massive-MIMO 시스템의 반복 검출 및 복호 수신기)

  • Park, Jin Soo;Kim, Inseon;Song, Hong-Yeop;Han, Sung Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39A no.9
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    • pp.528-534
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    • 2014
  • In this paper, we propose an iterative detection and decoding scheme for the LDPC coded multiuser uplink massive-MIMO systems. We consider the simple maximal ratio combining (MRC) detector and LDPC decoder. We formulate the soft output of MRC detector and the relation between the extrinsic informations of the detector and decoder. The performance improvement of the proposed iterative detection and decoding scheme is shown by computer simulation.