• Title, Summary, Keyword: Metal-oxide semiconductor field effect transistor

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Graphene field-effect transistor for radio-frequency applications : review

  • Moon, Jeong-Sun
    • Carbon letters
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    • v.13 no.1
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    • pp.17-22
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    • 2012
  • Currently, graphene is a topic of very active research in fields from science to potential applications. For various radio-frequency (RF) circuit applications including low-noise amplifiers, the unique ambipolar nature of graphene field-effect transistors can be utilized for high-performance frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with complementary metal-oxide-semiconductor compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene metal-oxide-semiconductor field-effect transistors to minimize parasitics and improve gate modulation efficiency in the channel. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antenna, where its success depends on quality of materials. We also attempt to discuss future applications and challenges of graphene.

Macro Modeling and Parameter Extraction of Lateral Double Diffused Metal Oxide Semiconductor Transistor

  • Kim, Sang-Yong;Kim, Il-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.1
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    • pp.7-10
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    • 2011
  • High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

Transient Characteristic of a Metal-Oxide Semiconductor Field Effect Transistor in an Automotive Regulator in High Temperature Surroundings

  • Kang, Chae-Dong;Shin, Kye-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.4
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    • pp.178-181
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    • 2010
  • An automotive IC voltage regulator which consists of one-chip based on a metal-oxide semiconductor field effect transistor (MOSFET) is investigated experimentally with three types of packaging. The closed type is filled with thermal silicone gel and covered with a plastic lid on the MOSFET. The half-closed type is covered with a plastic case but without thermal silicone gel on the MOSFET. Opened type is no lid without thermal silicone gel. In order to simulate the high temperature condition in engine bay, the operating circuit of the MOSFET is constructed and the surrounding temperature is maintained at $100^{\circ}C$. In the overshoot the maximum was mainly found at the half-closed packaging and the magnitude is dependent on the packaging type and the surrounding temperature. Also the impressed current decreased exponentially during the MOSFET operation.

Deformation of the AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistor characteristics by UV irradiation

  • Lim, Jin Hong;Kim, Jeong Jin;Yang, Jeon Wook
    • Journal of IKEEE
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    • v.17 no.4
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    • pp.531-536
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    • 2013
  • The impact of UV irradiation process on the AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistor was investigated. Due to the high intensity UV irradiation before the gate dielectric deposition, the conductivity of AlGaN/GaN structure and the drain saturation current of the transistor increased by about 10 %. However, the pinch off characteristics of transistor was severely deformed by the process. By comparing the electrical characteristics of the transistors, it was proposed that the high intensity UV irradiation formed a sub-channel under the two dimensional electron gas of AlGaN/GaN structure even without additional impurity injection.

A Novel Body-tied Silicon-On-Insulator(SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode

  • Kang, Won-Gu;Lyu, Jong-Son;Yoo, Hyung-Joun
    • ETRI Journal
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    • v.17 no.4
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    • pp.1-12
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    • 1996
  • A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

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High Performance Current Sensing Circuit for Current-Mode DC-DC Buck Converter

  • Jin, Hai-Feng;Piao, Hua-Lan;Cui, Zhi-Yuan;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.1
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    • pp.24-28
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    • 2010
  • A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

Device Optimization of N-Channel MOSFETs with Lateral Asymmetric Channel Doping Profiles

  • Baek, Ki-Ju;Kim, Jun-Kyu;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.1
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    • pp.15-19
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    • 2010
  • In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

Effect of Dopants on Cobalt Silicidation Behavior at Metal-oxide-semiconductor Field-effect Transistor Sidewall Spacer Edge

  • Kim, Jong-Chae;Kim, Yeong-Cheol;Kim, Byung-Kook
    • Journal of the Korean Ceramic Society
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    • v.38 no.10
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    • pp.871-875
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    • 2001
  • Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

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Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate

  • Ali, Asif;Seo, Dongsun;Cho, Il Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.1
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    • pp.156-161
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    • 2017
  • This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

  • Kim, Yong-Bin
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.5
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    • pp.175-188
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    • 2011
  • As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.