• Title, Summary, Keyword: Microwave Transceivers

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Microfabrication of Microwave Transceivers for On-Chip Near-Field Electromagnetic Shielding Characterization of Electroplated Copper Layers (극소형 전자기파 송수신기의 제작 및 전기도금된 구리박막의 칩단위 근접 전자기장 차폐효과 분석)

  • Gang, Tae-Gu;Jo, Yeong-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.25 no.6
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    • pp.959-964
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    • 2001
  • An experimental investigation on the near-field electromagnetic loss of thin copper layers has been presented using microfabricated microwave transceivers for applications to multi-chip microsystems. Copper layers in the thickness range of 0.2$\mu$m∼200$\mu$m have been electroplated on the Pyrex glass substrates. Microwave transceivers have been fabricated using the 3.5mm$\times$3.5mm nickel microloop antennas, electroformed on the silicon substrates. Electromagnetic radiation loss of the copper layers placed between the microloop transceivers has been measured as 10dB∼40dB for the wave frequency range of 100MHz∼1GHz. The 0.2$\mu$m-thick copper layer provides a shield loss of 20dB at the frequencies higher than 300MHz, whereas showing a predominant decreases of shield loss to 10dB at lower frequencies. No substantial increase of the shield effectiveness has been found for the copper shield layers thicker that 2 $\mu$m.

Fabrication of Tomography System Using Microwave Multi-Channel Transceiver (전자파 기반 다채널 토모그래피 테스트베드 제작)

  • Kim, Hyuk-Je;Lee, Jong-Moon;Lee, Youn-Ju;Son, Seong-Ho;Jeon, Soon-Ik
    • Proceedings of the IEEK Conference
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    • pp.1093-1094
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    • 2008
  • A tomography system using microwave multi-channel transceiver was fabricated and measured. The tomography system is applicable to detection of breast cancers in a human body. This system is configured by microwave muiti-channel transceivers, a illumination chamber housing monopole antennas and coupling liquid, and image reconstruction algorithm solving inverse scattering problem.

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Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals

  • Gutmann, R.J.;Zeng, A.Y.;Devarajan, S.;Lu, J.Q.;Rose, K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.196-203
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    • 2004
  • A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.