• Title, Summary, Keyword: Non-volatile Memory

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Design Space Exploration of EEPROM-SRAM Hybrid Non-volatile Counter Considering Energy Consumption and Memory Endurance (에너지 소비 및 메모리 내구성을 고려한 EEPROM-SRAM 하이브리드 비휘발성 카운터의 설계 공간 탐색)

  • Shin, Donghwa
    • IEMEK Journal of Embedded Systems and Applications
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    • v.11 no.4
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    • pp.201-208
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    • 2016
  • Non-volatile counter is a counter that maintains the value without external power supply. It has been used for the applications related to warranty issues to count and record certain events such as power cycles, operating time, hard resets, and timeouts. It has been conventionally implemented with volatile memory-based counter and battery backup or non-volatile memory such as EEPROM. Both of them have a lifetime issue due to the limited lifetime of the battery and the endurance of the non-volatile memory cells, which incurs significant redundancy in design. In this paper, we introduce a hybrid architecture of volatile (SRAM) and non-volatile memory (EEPROM) cells to achieve required lifetime of the non-volatile counter with smaller cost. We conduct a design space exploration of the proposed hybrid architecture with the parameters of various kinds of non-volatile memories. The analysis result shows that the proposed hybrid non-volatile counter can extend the lifetime up to 6 times compared to the battery-backup volatile memory-based implementation.

An Reliable Non-Volatile Memory using Alloy Nano-Dots Layer with Extremely High Density

  • Lee, Gae-Hun;Kil, Gyu-Hyun;An, Ho-Joong;Song, Yun-Heup
    • Proceedings of the Korean Vacuum Society Conference
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    • pp.241-241
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    • 2010
  • New non-volatile memory with high density and high work-function metal nano-dots, MND (Metal Nano-Dot) memory, was proposed and fundamental characteristics of MND capacitor were evaluated. In this work, nano-dot layer of FePt with high density and high work-function (~5.2eV) was fabricated as a charge storage site in non-volatile memory, and its electrical characteristics were evaluated for the possibility of non-volatile memory in view of cell operation by Fowler-Nordheim (FN)-tunneling. Here, nano-dot FePt layer was controlled as a uniform single layer with dot size of under ~ 2nm and dot density of ${\sim}\;1.2{\times}10^{13}/cm^2$. Electrical measurements of MOS structure with FePt nano-dot layer shows threshold voltage window of ~ 6V using FN programming and erasing, which is satisfied with operation of the non-volatile memory. Furthermore, this structure provides better data retention characteristics compared to other metal dot materials with the similar dot density in our experiments. From these results, it is expected that this non-volatile memory using FePt nano-dot layer with high dot density and high work-function can be one of candidate structures for the future non-volatile memory.

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A Non-volatile Memory Lifetime Extension Scheme Based on the AUTOSAR Platform using Complex Device Driver (AUTOSAR 플랫폼 기반 CDD를 활용한 비휘발성 메모리 수명 연장 기법)

  • Shin, Ju-Seok;Son, Jeong-Ho;Lee, Eun-Ryung;Oh, Se-Jin;Ahn, Kwang-Seon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.8 no.5
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    • pp.235-242
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    • 2013
  • Recently, the number of automotive electrical and electronic system has been increased because the requirements for the convenience and safety of the drivers and passengers are raised. In most cases, the data for controlling the various sensors and automotive electrical and electronic system used in runtime should be stored on the internal or external non-volatile memory of the ECU(Electronic Control Units). However, the non-volatile memory has a constraint with write limitation due to the hardware characteristics. The limitation causes fatal accidents or unexpected results if the non-volatile memory is not managed. In this paper, we propose a management scheme for using non-volatile memory to prolong the writing times based on AUTOSAR(AUTOmotive Open System Architecture) platform. Our proposal is implemented on the CDD(Complex Device Driver) and uses an algorithm which swaps a frequently modified block for a least modified block. Through the development of the prototype, the proposed scheme extends the lifetime of non-volatile memory about 1.08 to 2.48 times than simply using the AUTOSAR standard.

Performance and Energy Optimization for Low-Write Performance Non-volatile Main Memory Systems (낮은 쓰기 성능을 갖는 비휘발성 메인 메모리 시스템을 위한 성능 및 에너지 최적화 기법)

  • Jung, Woo-Soon;Lee, Hyung-Gyu
    • IEMEK Journal of Embedded Systems and Applications
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    • v.13 no.5
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    • pp.245-252
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    • 2018
  • Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.

Quantitative Analysis of Power Consumption for Low Power Embedded System by Types of Memory in Program Execution (저전력 임베디드 시스템을 위한 프로그램이 수행되는 메모리에 따른 소비전력의 정략적인 분석)

  • Choi, Hayeon;Koo, Youngkyoung;Park, Sangsoo
    • Journal of Korea Multimedia Society
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    • v.19 no.7
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    • pp.1179-1187
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    • 2016
  • Through the rapid development of latest hardware technology, high performance as well as miniaturized size is the essentials of embedded system to meet various requirements from the society. It raises possibilities of genuine realization of IoT environment whose size and battery must be considered. However, the limitation of battery persistency and capacity restricts the long battery life time for guaranteeing real-time system. To maximize battery life time, low power technology which lowers the power consumption should be highly required. Previous researches mostly highlighted improving one single type of memory to increase ones efficiency. In this paper, reversely, considering multiple memories to optimize whole memory system is the following step for the efficient low power embedded system. Regarding to that fact, this paper suggests the study of volatile memory, whose capacity is relatively smaller but much low-powered, and non-volatile memory, which do not consume any standby power to keep data, to maximize the efficiency of the system. By executing function in specific memories, non-volatile and volatile memory, the quantitative analysis of power consumption is progressed. In spite of the opportunity cost of all of theses extra works to locate function in volatile memory, higher efficiencies of both power and energy are clearly identified compared to operating single non-volatile memory.

Adaptive Writeback-aware Cache Management Policy for Lifetime Extension of Non-volatile Memory

  • Hwang, Sang-Ho;Choi, Ju Hee;Kwak, Jong Wook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.4
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    • pp.514-523
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    • 2017
  • In this paper, we propose Adaptive Writeback-aware Cache management (AWC) to prolong the lifetime of non-volatile main memory systems by reducing the number of writebacks. The last-level cache in AWC is partitioned into Least Recently Used (LRU) segment and LRU using Dirty block Precedence (DP-LRU) segment. The DP-LRU segment evicts clean blocks first for giving reuse opportunity to dirty blocks. AWC can also determine the efficient size of DP-LRU segment for reducing the number of writebacks according to memory access patterns of programs. In the performance evaluation, we showed that AWC reduced the number of writebacks up to 29% and 46%, and saved the energy of a main memory system up to 23% and 49% in a single-core and multi-core, respectively. AWC also reduced the runtime by 1.5% and 3.2% on average compared to previous cache managements for non-volatile main memory systems, in a single-core and a multi-core, respectively.

Overview of the Current Status of Technical Development for a Highly Scalable, High-Speed, Non-Volatile Phase-Change Memory

  • Lee, Su-Youn;Jeong, Jeung-Hyun;Cheong, Byung-Ki
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.1-10
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    • 2008
  • The present status of technical development of a highly scalable, high-speed non-volatile PCM is overviewed. Major technical challenges are described along with solutions that are being pursued in terms of innovative device structures and fabrication technologies, new phase change materials, and new memory schemes.

Characterization and Improvement of Non-Volatile Dual In-Line Memory Module (NVDIMM의 동작 특성 분석 및 개선 방안 연구)

  • Park, Jaehyun;Lee, Hyung Gyu
    • IEMEK Journal of Embedded Systems and Applications
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    • v.12 no.3
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    • pp.177-184
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    • 2017
  • High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.

Energy Consumption Evaluation for Two-Level Cache with Non-Volatile Memory Targeting Mobile Processors

  • Matsuno, Shota;Togawa, Masashi;Yanagisawa, Masao;Kimura, Shinji;Sugibayashi, Tadahiko;Togawa, Nozomu
    • IEIE Transactions on Smart Processing and Computing
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    • v.2 no.4
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    • pp.226-239
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    • 2013
  • A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

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Performance Analysis of Adaptive Partition Cache Replacement using Various Monitoring Ratios for Non-volatile Memory Systems

  • Hwang, Sang-Ho;Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.23 no.4
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    • pp.1-8
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    • 2018
  • In this paper, we propose an adaptive partition cache replacement policy and evaluate the performance of our scheme using various monitoring ratios to help lifetime extension of non-volatile main memory systems without performance degradation. The proposal combines conventional LRU (Least Recently Used) replacement policy and Early Eviction Zone (E2Z), which considers a dirty bit as well as LRU bits to select a candidate block. In particular, this paper shows the performance of non-volatile memory using various monitoring ratios and determines optimized monitoring ratio and partition size of E2Z for reducing the number of writebacks using cache hit counter logic and hit predictor. In the experiment evaluation, we showed that 1:128 combination provided the best results of writebacks and runtime, in terms of performance and complexity trade-off relation, and our proposal yielded up to 42% reduction of writebacks, compared with others.