• Title, Summary, Keyword: Phase lock loop (PLL)

Search Result 87, Processing Time 0.041 seconds

A Fast Lock and Low Jitter Phase Locked Loop with Locking Status Indicator (Locking 상태 표시기를 이용한 저잡음 고속 위상고정 루프)

  • Choi Young-Shig;Han Dae-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.9 no.3
    • /
    • pp.582-586
    • /
    • 2005
  • This paper presents a new structure of Phase Locked Loop(PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and, Locking Status Indicator(LSI). The LSI decides the operating bandwidth of loop filler. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than $40{\mu}s$ and spur is 76.1dBc. It is simulated by HSPICE in a Hynix CMOS $0.35{\mu}m$ Process.

A New Phase-Locked Loop System with the Controllable Output Phase and Lock-up Time

  • Vibunjarone, Vichupong;Prempraneerach, Yothin
    • 제어로봇시스템학회:학술대회논문집
    • /
    • /
    • pp.1836-1840
    • /
    • 2003
  • This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

  • PDF

Design of Fractional-N Digital PLL for IoT Application (IoT 어플리케이션을 위한 분수분주형 디지털 위상고정루프 설계)

  • Kim, Shinwoong
    • Journal of IKEEE
    • /
    • v.23 no.3
    • /
    • pp.800-804
    • /
    • 2019
  • This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

A Fast Locking Dual-Loop PLL with Adaptive Bandwidth Scheme (루프 대역폭 조절기를 이용한 빠른 위상 고정 시간을 갖는 이중 루프 위상고정루프)

  • Song, Youn-Gui;Choi, Young-Shig
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.5
    • /
    • pp.65-70
    • /
    • 2008
  • A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

A Multiple Gain Controlled Digital Phase and Frequency Detector for Fast Lock-Time (빠른 Lock-Time을 위한 다중 이득 제어 디지털 위상 주파수 검출기)

  • Hong, Jong-Phil
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.51 no.2
    • /
    • pp.46-52
    • /
    • 2014
  • This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

A Robust PLL Technique Based on the Digital Lock-in Amplifier under the Non-Sinusoidal Grid Conditions (디지털 록인앰프를 이용한 비정현 계통하에서 강인한 PLL 방법)

  • Ashraf, Muhammad Noman;Khan, Reyyan Ahmad;Choi, Woojin
    • Proceedings of the KIPE Conference
    • /
    • /
    • pp.104-106
    • /
    • 2018
  • The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

  • PDF

Design of a PLL Frequency Synthesizer for RSSI Applications Using Phase Noise Analysis (위상잡음 해석을 이용한 RSSI용 PLL 주파수합성기 설계)

  • Kim, Nam-Tae;Jeong, Jae-Han;Song, Han-Jung
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.48 no.12
    • /
    • pp.28-34
    • /
    • 2011
  • In this paper, a PLL frequency synthesizer for RSSI applications is designed by phase noise analysis. Required synthesizer performance is achieved by optimizing the noise performance of PLL components and a loop transfer function, since its phase noise, lock time, and spur suppression capability are determined by the performance of loop components and loop filter characteristics. As an application example, a PLL frequency synthesizer for RSSI applications, which operates at the frequency of 2.288GHz, is designed using the phase noise analysis. The validity of the design technique is proved by experiments.

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

  • Lee, Kwang-Hun;Jang, Young-Chan
    • Journal of information and communication convergence engineering
    • /
    • v.10 no.2
    • /
    • pp.187-193
    • /
    • 2012
  • A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

An Analytical Approximation for the Pull-Out Frequency of a PLL Employing a Sinusoidal Phase Detector

  • Huque, Abu-Sayeed;Stensby, John
    • ETRI Journal
    • /
    • v.35 no.2
    • /
    • pp.218-225
    • /
    • 2013
  • The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

A Method to Improve the Performance of Phase-Locked Loop (PLL) for a Single-Phase Inverter Under the Non-Sinusoidal Grid Voltage Conditions (비정현 계통 전압하에서 단상 인버터의 PLL 성능 개선 방법)

  • Khan, Reyyan Ahmad;Ashraf, Muhammad Noman;Choi, Woojin
    • Proceedings of the KIPE Conference
    • /
    • /
    • pp.7-8
    • /
    • 2017
  • The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

  • PDF