• Title, Summary, Keyword: Redundant Binary

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A Design of Radix-2 SRT Floating-Point Divider Unit using ]Redundant Binary Number System (Redundant Binary 수치계를 이용한 radix-2 SRT부동 소수점 제산기 유닛 설계)

  • 이종남;신경욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.5 no.3
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    • pp.517-524
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    • 2001
  • This paper describes a design of radix-2 SRT divider unit, which supports IEEE-754 floating-point standard, using redundant binary number system (RBNS). With the RBNS, the partial quotient decision logic can operate about 20-% faster, as well as can be implemented with a simple hardware when compared to the conventional methods based on two's complement arithmetic. By using a new redundant binary adder proposed in this paper, the mantissa divider is efficiently implemented, thus resulting in about 20% smaller area than other works. The divider unit supports double precision format, five exceptions and four rounding modes. It was verified with Verilog HDL and Verilog-XL.

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A Design of 16${\times}$16-bit Redundant Binary MAC Using 0.25 ${\mu}{\textrm}{m}$ CMOS Technology

  • Kim, Tae-Min;Shin, Gun-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.1
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    • pp.122-128
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    • 2003
  • In this paper, a 16${\times}$16-bit Multiplier and Accumulator (MAC) is designed using a Redundant Binary Adder (RBA) circuit so that it can make a fast addition of the Redundant Binary Partial Products (RB_PP's) by using Wallace-tree structure. Because a RBA adds two RB numbers, it acts as a 4-2 compressor, which reduces four inputs to two output signals. We propose a method to convert the Redundant Binary (RB) representation into the 2's complement binary representation. Instead of using the conventional full adders, a more efficient RB number to binary number converter can be designed with new conversion method.

A Design of the Redundant Binary Coded Decimal Adder for the Carry-Free Binary Coded Decimal Addition (Redundant 십진코드를 이용하여 십진 자리간 Carry 전파를 제거한 십진 Adder 설계)

  • Je, Jung-Min;Chung, Tae-Sang
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.55 no.11
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    • pp.491-494
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    • 2006
  • In the adder design, reduction of the delay of the carry propagation or ripple is the most important consideration. Previously, it was introduced that, if a redundant number system is adopted, the carry propagation is completely eliminated, with which addition can be done in a constant time, without regarding to the count of the digits of numbers involved in addition. In this paper, a RBCD(Redundant Binary Coded Decimal) is adopted to code 0 to 11, and an efficient and economic carry-free BCD adder is designed.

Design of a High Speed and Low Power CMOS Demultiplexer Using Redundant Multi-Valued Logic (Redundant Multi-Valued Logic을 이용한 고속 및 저전력 CMOS Demultiplexer 설계)

  • Kim, Tae-Sang;Kim, Jeong-Beom
    • Proceedings of the KIEE Conference
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    • pp.148-151
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    • 2005
  • This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

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The CORDIC Circuit of Redundant Signed Binary Number (Redundant Signed Binary Number에 의한 CORDIC 회로)

  • 김승열;김용대;한선경;유영갑
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.40 no.6
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    • pp.1-8
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    • 2003
  • A novel CORDIC circuit is presented based on a redundant number system eliminating global carry Propagation. The number format employs a new recoding scheme similar to the Booth receding resolving carry problems in addition. A pipelined architecture is introduced having a constant scale factor in its computation of trigonometric functions. The operational time of the circuit is constant independent of the number of operand digits.

A Design and Fabrication of the High-Speed Division/square-Root using a Redundant Floating Point Binary Number (고속 여분 부동 소수점 이진수의 제산/스퀘어-루트 설계 및 제작)

  • 김종섭;이종화;조상복
    • Proceedings of the IEEK Conference
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    • pp.365-368
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    • 2001
  • This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

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Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic (중복 다치논리를 이용한 20 Gb/s CMOS 디멀티플렉서 설계)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.3
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    • pp.135-140
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    • 2008
  • This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

A high-speed complex multiplier based on redundant binary arithmetic (Redundant binary 연산을 이용한 고속 복소수 승산기)

  • 신경욱
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.2
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    • pp.29-37
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    • 1997
  • A new algorithm and parallel architecture for high-speed complex number multiplication is presented, and a prototype chip based on the proposed approach is designed. By employing redundant binary (RB) arithmetic, an N-bit complex number multiplication is simplified to two RB multiplications (i.e., an addition of N RB partial products), which are responsible for real and imaginary parts, respectively. Also, and efficient RB encoding scheme proposed in this paper enables to generate RB partial products without additional hardware and delay overheads compared with binary partial product generation. The proposed approach leads to a highly parallel architecture with regularity and modularity. As a results, it results in much simpler realization and higher performance than the classical method based on real multipliers and adders. As a test vehicle, a prototype 8-b complex number multiplier core has been fabricated using $0.8\mu\textrm{m}$ CMOS technology. It contains 11,500 transistors on the area of about $1.05 \times 1.34 textrm{mm}^2$. The functional and speed test results show that it can safely operate with 200 MHz clock at $V_{DD}=2.5 V$, and consumes about 90mW.

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Design of a 9 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued logic (Redundant 다치논리 (Multi-Valued Logic)를 이용한 9 Gb/s CMOS 디멀티플렉서 설계)

  • Ahn, Sun-Hong;Kim, Jeong-Beom
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.121-126
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    • 2007
  • This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

A design of Adaptive Decision-feedback Equalizer Module using Redundant Binary Complex Filter (Redundant Binary 복소수 필터를 이용한 적응 결정귀환 등화기 모듈 설계)

  • 김호하;안병규신경욱
    • Proceedings of the IEEK Conference
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    • pp.1125-1128
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    • 1998
  • A new architecture for high-speed implementation of adaptive decision-feedback equalizer (ADFE) applicable to wide-band digital wireless modems is described. Rather than using conventional two's complement arithmetic, a novel complex-valued filter structure is devised, which is based on redundant binary (RB) arithmetic. The proposed RB complex-valued filter reduces the critical path delay of ADFE, as well as leads to a more compact implementation than conventional methods. Also, the carry-propagation free (CPF) operation of the RB arithmetic enhances its speed. To demonstrate the proposed method, a prototype chip set is designed. They are designed to contain two complexvalued filter taps along with their coefficient updating circuits, and can be cascaded to implement loger filter taps for high bit-rate applications.

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