• Title, Summary, Keyword: Scan cells

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Verification of System using Master-Slave Structure (Master-Slave 기법을 적용한 System Operation의 동작 검증)

  • Kim, In-Soo;Min, Hyoung-Bok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.1
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    • pp.199-202
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    • 2009
  • Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

A New Scan Partition Scheme for Low-Power Embedded Systems

  • Kim, Hong-Sik;Kim, Cheong-Ghil;Kang, Sung-Ho
    • ETRI Journal
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    • v.30 no.3
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    • pp.412-420
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    • 2008
  • A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

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Low Power Test for SoC(System-On-Chip)

  • Jung, Jun-Mo
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.729-732
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    • 2011
  • Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

A Study on Repair of Scan Design Rule Violations at Clock and Reset Pins of Scan Cells (스캔셀의 Clock과 Reset핀에서의 스캔 설계 Rule Violations 방지를 위한 설계 변경)

  • Kim, In-Soo;Min, Hyoung-Bok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.2
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    • pp.93-101
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    • 2003
  • Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. The scan design cannot be used in a design with scan design rule violations without modifying the design. The most important scan design rule is concerning clock and reset signals to pins of the flip-flops or scan cells. Clock and Reset pins of every scan cell must be controllable from top-level ports. We propose a new technique to re-design gated clocks and resets which violate the scan design rule concerning the clock and reset pins. This technique substitutes synchronous sequential circuits for gated clock and reset designs, which removes the clock and reset rule violations and improves fault coverage of the design. The fault coverage is improved from $90.48\%$ to $100.00\%$, from $92.31\%$ to $100.00\%$, from $95.45\%$ to $100.00\%$, from $97.50\%$ to $100.00\%$ in a design with gated clocks and resets.

A Grouped Scan Chain Reordering Method for Wire Length Minimization (배선 길이 최소화를 위한 그룹화된 스캔 체인 재구성 방법)

  • Lee, Jeong-Hwan;Im, Jong-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.8
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    • pp.74-83
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    • 2002
  • In order to design a huge VLSI system, the scan testing methodology by employing scan flip-flops(cells) is a popular method to test those If chips. In this case, the connection order of scan cells are not important, and hence the order can be determined in the very final stage of physical design such as cell placement. Using this fact, we propose, in this paper, a scan cell reordering method which minimizes the length of wires for scan chain connections. Especially, our reordering method is newly proposed method in the case when the scan cells are grouped according to their clock domains. In fact, the proposed reordering method reduces the wire length about 13.6% more than that by previously proposed reordering method. Our method may also be applicable for reordering scan chains that have various constraints on the scan cell locations due to the chain grouping.

A New Scan Chain Fault Simulation for Scan Chain Diagnosis

  • Chun, Sung-Hoon;Kim, Tae-Jin;Park, Eun-Sei;Kang, Sung-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.4
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    • pp.221-228
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    • 2007
  • In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

Low Power Test for SoC(System-On-Chip)

  • Jung, Jun-Mo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.892-895
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    • 2011
  • Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

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Scan Cell Grouping Algorithm for Low Power Design

  • Kim, In-Soo;Min, Hyoung-Bok
    • Journal of Electrical Engineering and Technology
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    • v.3 no.1
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    • pp.130-134
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    • 2008
  • The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

New IEEE 1149.1 Boundary Scan Architecture for Multi-drop Multi-board System (멀티 드롭 멀티 보드 시스템을 위한 새로운 IEEE 1149.1 경계 주사 구조)

  • Bae, Sang-Min;Song, Dong-Sup;Kang, Sung-Ho;Park, Young-Ho
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.49 no.11
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    • pp.637-642
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    • 2000
  • IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

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A New Method for the Test Scheduling in the Boundary Scan Environment (경계 주사 환경에서의 상호연결 테스트 방법론에 대한 연구)

  • Kim, Hyun-Jin;Shin, Jong-Chul;Kang, Sung-Ho
    • Proceedings of the KIEE Conference
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    • pp.669-671
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    • 1998
  • Due to the serial nature of scan chains, the use of the boundary scan chain leads the high application costs. And with 3-state net, it is important to avoid enabling the two drivers in a net. In this paper, the new test method for 3-state nets in the multiple boundary scan chains is presented. This method configures the boundary scan cells as multiple scan chains and the test application time can be reduced. Also three efficient algorithms are proposed for testing the interconnects in a board without the collision of the test data in 3-state nets.

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