• Title, Summary, Keyword: Short line fault

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Characterization Method for Testing Circuit Patterns on MCM/PCB Modules with Electron Beams of a Scanning Electron Microscope (MCM/PCB 회로패턴 검사에서 SEM의 전자빔을 이용한 측정방법)

  • Kim, Joon-Il;Shin, Joon-Kyun;Jee, Yong
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.9
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    • pp.26-34
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    • 1998
  • This paper presents a characterization method for faults of circuit patterns on MCM(Multichip Module) or PCB(Printed Circuit Board) substrates with electron beams of a SEM(Scanning Electron Microscope) by inducing voltage contrast on the signal line. The experimentation employes dual potential electron beams for the fault characterization of circuit patterns with a commercial SEM without modifying its structure. The testing procedure utilizes only one electron gun for the generation of dual potential electron beams by two different accelerating voltages, one for charging electron beam which introduces the yield of secondary electron $\delta$ < 1 and the other for reading beam which introduces $\delta$ > 1. Reading beam can read open's/short's of a specific net among many test nets, simultaneously discharging during the reading process for the next step, by removing its voltage contrast. The experimental results of testing the copper signal lines on glass-epoxy substrates showed that the state of open's/short's had generated the brightness contrast due to the voltage contrast on the surface of copper conductor line, when the net had charged with charging electron beams of 7KV accelerating voltages and then read with scanning reading electron beams of 2KV accelerating voltages in 10 seconds. The experimental results with Au pads of a IC die and Au plated Cu pads of BGA substrates provided the simple test method of circuit lines with 7KV charging electron beam and 2KV reading beam. Thus the characterization method showed that we can test open and short circuits of the net nondestructively by using dual potential electron beams with one SEM gun.

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Current Limiting and Interrupting Operation of Hybrid Self-Excited Type Superconducting DCCB

  • Choi, S.J.;Lim, S.H.
    • Progress in Superconductivity and Cryogenics
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    • v.20 no.4
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    • pp.55-59
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    • 2018
  • Currently, the development of industry makes needs larger electric supply. Providers must consider the efficiency about losses and reliability of the system. In this case, DC power system can save electrical energy; long-distance transmission line losses. Relevance to switch technology with a voltage-source converter (VSC) in AC-DC conversion system have been researched. But, protection device of DC-link against fault current is still needed to study much. VSC DC power system is vulnerable to DC-cable short-circuit and ground faults, because DC-link has a huge size of capacitor filter which releases extremely large current during DC faults. Furthermore, DC has a fatal flaw that current zero crossing is nonexistence. To interrupt the DC, several methods which make a zero crossing is used; parallel connecting self-excited series LC circuit with main switch, LC circuit with power electronic device called hybrid DC circuit breaker. Meanwhile, self-excited oscillator needs a huge size capacitor that produces big oscillation current which makes zero crossing. This capacitor has a quite effective on the price of DCCB. In this paper, hybrid self-excited type superconducting DCCB which are using AC circuit breaker system is studied by simulation tool PSCAD/EMTDC.

A Study on Development of Scaled-down HVDC Model (HVDC의 축소형 모델 개발에 관한 연구)

  • Ahn, Jong-Bo;Yun, Jae-Young;Kim, Kook-Hun;Lee, Jong-Moo;Kim, Jong-Moon;Lee, Ki-Do
    • Proceedings of the KIEE Conference
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    • pp.219-221
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    • 1999
  • HVDC(High Voltage Direct Current) transmission system was constructed between Cheju island and mainland Haenam and has been operating commercially since 1998. But research activities in this area are not so much. That is caused by the facts that HVDC is large scale system and it is not so easy to implement and to test. Though such simulation tools as RTDS(Real Time Digital Simulator) and EMTDC can be useful, these have limitations for actual control and protective system design. Therefore scaled-down HVDC model was developed for the purpose of researches at operating technique, control and protection methods. The design of this model was based on real Cheju-Haenam HVDC system. And additionally faults simulator such as ground fault, short-circuit and change of impedance in transmission line is equipped for analysis of these faults. Control system of the model was implemented fully digitally. So it is very easy for the researchers to develope control and protection algorithm and to test the performance.

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The Calculation Method with index for the Transfer Power limit to Capital Area (지수를 적용한 수도권 융통전력한계량 계산)

  • Lee, Woon-Hee;Kang, Myung-Jang;Song, Suk-Ha
    • Proceedings of the KIEE Conference
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    • pp.50-52
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    • 2008
  • We have limited the transfer power to capital area below a certain level which is called "The Capital Area Transfer Power Limit", and calculated on every Thursday for the application next week. This level is very important in our network operation, because if this level is not set properly, our power network can be fallen under great danger in case of a fault among the transfer power line. But the calculation procedure for the limit level is so complicated and iterative that it mace us spend much time and do much work. So, when a sudden trip of the related facility to the limit level we can't recalculate the limit level fast enough. And this can drop our network reliability below our standards, therefore our network can be dangerous. To avoid this kind of problems, we have figured out a method to calculate simply the limit level. That method uses the index related to the level. We think this method can make short of the calculation procedures for the level. This paper deals with the simplified method for the calculation of the level limit.

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A Study on the Imfluence of the Pipe Line of Boiler for Flame Distribution of Combustion Furnace (연소로의 화염분포가 보일러 관로에 미치는 영향에 관한 연구)

  • Cho, Dong-Hyun
    • Journal of Fisheries and Marine Sciences Education
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    • v.26 no.6
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    • pp.1435-1441
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    • 2014
  • The fire took place in the synthetic heat transfer fluid boiler used in production process of medium density fiberboard. This study investigated pressure distribution of the first, second and third passes and the temperature in the fire burner. The boiler's internal fluid is unsteady due to the out of order inverter. As the operation continues, the flame's flow and speed are unsteady. The synthetic heat transfer fluid leak spouted about 120kg/min in the form of vapor in the early period of the fire. The flame extended to the second and third passes. The highest temperature of the second and third pass is $1059^{\circ}C$ and $1007^{\circ}C$, respectively. The synthetic heat transfer fluid spouted through the cracked part of the fire box in the first pass and accumulated on the turn table. Therefore, it is expected that the temperature of the interior of the fire box is above $1200^{\circ}C$. The temperature of the burner rises to a maximum level several times in a short period. On account of that, several explosions occur in the fire burner. Pressure distribution at steady state in combustion furnace is 2~5mAq and pressure distribution at inverter under fault condition in combustion furnace is 10~-53mAq. The decrement of coil thickness measurement for synthetic heat transfer fluid boiler is 0~5mm.

A Study on the Test Strategy of Digital Circuit Board in the Production Line Based on Parallel Signature Analysis Technique (PSA 기법에 근거한 생산라인상의 디지털 회로 보오드 검사전략에 대한 연구)

  • Ko Yun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.11
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    • pp.768-775
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    • 2004
  • The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.