• Title, Summary, Keyword: Switching activity

### A Low Poorer Resource Allocation Algorithm Based on Minimizing Switching Activity (스위칭 동작 최소화를 통한 저 전력 자원할당 알고리즘)

• 신무경;인치호;김희석
• Proceedings of the IEEK Conference
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• pp.121-124
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• 2001
• This paper proposed resource allocation algorithm for the minimum switching activity of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. The resource allocation method after scheduling use the power function calculating average hamming distance and switching activity of the between two input. First of all, the switching activity is calculated by the input value after calculating the average hamming distance between operation. In this paper, the proposed method though high If level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and max control step. And it is the reduction effect from 6% to 8%.

### A Low Power Resource Allocation Algorithm based on Minimizing Switching Activity (스위칭 동작 최소화를 통한 저 전력 자원할당 알고리즘)

• Lin, Chi-Ho
• Journal of IKEEE
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• v.10 no.2
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• pp.103-108
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• 2006
• This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

### Reduction of Power Dissipation by Switching Activity Restriction in Pipeline datapaths (파이프라인 데이터경로에서의 스위칭 동작 제한을 통한 전력소모 축소)

• 정현권;김진주;최명석;김동욱
• Proceedings of the IEEK Conference
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• pp.381-384
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• 1999
• In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.

### A High-Level Data Path Allocation Algorithm for Low Power Architecture (저 전력 아키텍처를 위한 상위 레벨 데이터 패스 할당 알고리즘)

• Lin, Chi-Ho
• Journal of IKEEE
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• v.7 no.2
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• pp.166-171
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• 2003
• In this paper, we propose a minimal power data path allocation algorithm for low power circuit design. The proposed algorithm minimizes switching activity for input variables in scheduled CDFG. Allocations are further divided into the tasks of register allocation and module allocation. The register allocation algorithm execute that it eliminate spurious switching activity in functional unit and minimize the numbers of multiplexer. Also, resource allocation method selects a sequence of operations for a module such that the switching activity is reduced. Therefore, the algorithm executes to minimize the switching activity of input values, sequence of operations and number of multiplexer. Experimental results using benchmarks show that power is reduction effect from 13% to 17% power consumption, when compared with the Genesis-lp high-level synthesis system.

### Instruction addressing method and implemetation for low pouter system by using guarded operation (Guarded Operation을 이용한 명령어 어드레싱 방법 및 구현)

• 이세환;곽승호;이문기
• Proceedings of the IEEK Conference
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• pp.345-348
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• 2001
• In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.

### A New Resource Allocation Algorithm for Low Power Architecture (저 전력 아키텍처 설계를 위한 새로운 자원할당 알고리즘)

• 신무경;인치호
• Proceedings of the IEEK Conference
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• pp.329-332
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• 2000
• This paper proposed resource allocation algorithm for the minimum power consumption of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. In this paper, the proposed method though high level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To used the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step.

### A New High speed, Low Power TFT-LCD Driving Method (새로운 고속, 저전력 TFT-LCD 구동 방법)

• Park, Soo-Yang;Son, Sang-Hee;Chung, Won-Sup
• Journal of IKEEE
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• v.10 no.2
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• pp.134-140
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• 2006
• This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

### A Novel High Performance Scan Architecture with Dmuxed Scan Flip-Flop (DSF) for Low Shift Power Scan Testing

• Kim, Jung-Tae;Kim, In-Soo;Lee, Keon-Ho;Kim, Yong-Hyun;Baek, Chul-Ki;Lee, Kyu-Taek;Min, Hyoung-Bok
• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.559-565
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• 2009
• Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

### Operation Rearrangement for Low-Power VLIW Instruction Fetches (저전력 VLIW 명령어 추출을 위한 연산재배치 기법)

• Sin, Dong-Gun;Kim, Ji-Hong
• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.530-540
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• 2001
• As mobile applications are required to handle more computing-intensive tasks, many mobile devices are designed using VLIW processors for high performance. In VLIW machines where a single instruction contains multiple operations, the power consumption during instruction fetches varies significantly depending on how the operations are arranged within the instruction. In this paper, we describe a post-pass optimal operation rearrangement method for low-power VLIW instruction fetch, The proposed method modifies operation placement orders within VLIW instructions so that the switching activity between successive instruction fetches is minimized. Our experiment shows that the switching activity can be 34% on average fro benchmark programs.

### SUMO Proteins are not Involved in TGF-${\beta}1$-induced, Smad3/4-mediated Germline ${\alpha}$ Transcription, but PIASy Suppresses it in CH12F3-2A B Cells

• Lee, Sang-Hoon;Kim, Pyeung-Hyeun;Oh, Sang-Muk;Park, Jung-Hwan;Yoo, Yung-Choon;Lee, Junglim;Park, Seok-Rae
• IMMUNE NETWORK
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• v.14 no.6
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• pp.321-327
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• 2014
• TGF-${\beta}$ induces IgA class switching by B cells. We previously reported that Smad3 and Smad4, pivotal TGF-${\beta}$ signal-transducing transcription factors, mediate germline (GL) ${\alpha}$ transcription induced by TGF-${\beta}1$, resulting in IgA switching by mouse B cells. Post-translational sumoylation of Smad3 and Smad4 regulates TGF-${\beta}$-induced transcriptional activation in certain cell types. In the present study, we investigated the effect of sumoylation on TGF-${\beta}1$-induced, Smad3/4-mediated $GL{\alpha}$ transcription and IgA switching by mouse B cell line, CH12F3-2A. Overexpression of small ubiquitin-like modifier (SUMO)-1, SUMO-2 or SUMO-3 did not affect TGF-${\beta}1$-induced, Smad3/4-mediated $GL{\alpha}$ promoter activity, expression of endogenous $GL{\alpha}$ transcripts, surface IgA expression, and IgA production. Next, we tested the effect of the E3 ligase PIASy on TGF-${\beta}1$-induced, Smad3/4-mediated $GL{\alpha}$ promoter activity. We found that PIASy overexpression suppresses the $GL{\alpha}$ promoter activity in cooperation with histone deacetylase 1. Taken together, these results suggest that SUMO itself does not affect regulation of $GL{\alpha}$ transcription and IgA switching induced by TGF-${\beta}1$/Smad3/4, while PIASy acts as a repressor.