• Title, Summary, Keyword: Symmetric and asymmetric topology

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A New Family of Cascaded Transformer Six Switches Sub-Multilevel Inverter with Several Advantages

  • Banaei, M.R.;Salary, E.
    • Journal of Electrical Engineering and Technology
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    • v.8 no.5
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    • pp.1078-1085
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    • 2013
  • This paper presents a novel topology for cascaded transformer sub-multilevel converter. Eachsub-multilevel converter consists of two DC voltage sources with six switches to achieve five-level voltage. The proposed topology results in reduction of DC voltage sources and switches number. Single phase low frequency transformers are used in proposed topology and voltage transformation and galvanic isolation between load and sources are given by transformers. This topology can operate as symmetric or asymmetric converter but in this paper we have focused on symmetric state. The operation and performance of the suggested multilevel converter has been verified by the simulation results of a single-phase nine-level multilevel converter using MATLAB/SIMULINK.

Advanced Cascade Multilevel Converter with Reduction in Number of Components

  • Ajami, Ali;Oskuee, Mohammad Reza Jannati;Mokhberdoran, Ataollah;Khosroshahi, Mahdi Toupchi
    • Journal of Electrical Engineering and Technology
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    • v.9 no.1
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    • pp.127-135
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    • 2014
  • In this paper a novel converter structure based on cascade converter family is presented. The suggested multilevel advanced cascade converter has benefits such as reduction in number of switches and power losses. Comparison depict that proposed topology has the least number of IGBTs among all multilevel cascade type converters which have been introduced recently. This characteristic causes low cost and small installation area for suggested converter. The number of on state switches in current path is less than conventional topologies and so the output voltage drop and power losses are decreased. Symmetric and asymmetric modes are analyzed and compared with conventional multilevel cascade converter. Simulation and experimental results are presented to illustrate validity, good performance and effectiveness of the proposed configuration. The suggested converter can be applied in medium/high voltage and PV applications.

The Postorder Fibonacci Circulants-a new interconnection networks with lower diameter (후위순회 피보나치 원형군-짧은 지름을 갖는 새로운 상호연결망)

  • Kim Yong-Seok;Kwon Seung-Tag
    • Proceedings of the IEEK Conference
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    • pp.91-94
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    • 2004
  • In this paper, we propose a new parallel computer topology, called the postorder Fibonacci circulants and analyze its properties. It is compared with Fibonacci cubes, when its number of nodes and its degree is kept the same of comparable one. Its diameter is improved from n-2 to [$\frac{n}{3}$] and a its topology is changed from asymmetric to symmetric. It includes Fibonacci cube as a spanning tree.

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Asymmetric Cascaded Multi-level Inverter: A Solution to Obtain High Number of Voltage Levels

  • Banaei, M.R.;Salary, E.
    • Journal of Electrical Engineering and Technology
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    • v.8 no.2
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    • pp.316-325
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    • 2013
  • Multilevel inverters produce a staircase output voltage from DC voltage sources. Requiring great number of semiconductor switches is main disadvantage of multilevel inverters. The multilevel inverters can be divided in two groups: symmetric and asymmetric converters. The asymmetric multilevel inverters provide a large number of output steps without increasing the number of DC voltage sources and components. In this paper, a novel topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converters can produce five levels of voltage. Four algorithms for determining the DC voltage sources magnitudes have been presented. Finally, in order to verify the theoretical issues, simulation is presented.

Topology Aggregation Schemes for Asymmetric Link State Information

  • Yoo, Young-Hwan;Ahn, Sang-Hyun;Kim, Chong-Sang
    • Journal of Communications and Networks
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    • v.6 no.1
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    • pp.46-59
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    • 2004
  • In this paper, we present two algorithms for efficiently aggregating link state information needed for quality-of-service (QoS) routing. In these algorithms, each edge node in a group is mapped onto a node of a shufflenet or a node of a de Bruijn graph. By this mapping, the number of links for which state information is maintained becomes aN (a is an integer, N is the number of edge nodes) which is significantly smaller than N2 in the full-mesh approach. Our algorithms also can support asymmetric link state parameters which are common in practice, while many previous algorithms such as the spanning tree approach can be applied only to networks with symmetric link state parameters. Experimental results show that the performance of our shufflenet algorithm is close to that of the full-mesh approach in terms of the accuracy of bandwidth and delay information, with only a much smaller amount of information. On the other hand, although it is not as good as the shufflenet approach, the de Bruijn algorithm also performs far better than the star approach which is one of the most widely accepted schemes. The de Bruijn algorithm needs smaller computational complexity than most previous algorithms for asymmetric networks, including the shufflenet algorithm.

A Medium Access Control Mechanism for Distributed In-band Full-Duplex Wireless Networks

  • Zuo, Haiwei;Sun, Yanjing;Li, Song;Ni, Qiang;Wang, Xiaolin;Zhang, Xiaoguang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.11
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    • pp.5338-5359
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    • 2017
  • In-band full-duplex (IBFD) wireless communication supports symmetric dual transmission between two nodes and asymmetric dual transmission among three nodes, which allows improved throughput for distributed IBFD wireless networks. However, inter-node interference (INI) can affect desired packet reception in the downlink of three-node topology. The current Half-duplex (HD) medium access control (MAC) mechanism RTS/CTS is unable to establish an asymmetric dual link and consequently to suppress INI. In this paper, we propose a medium access control mechanism for use in distributed IBFD wireless networks, FD-DMAC (Full-Duplex Distributed MAC). In this approach, communication nodes only require single channel access to establish symmetric or asymmetric dual link, and we fully consider the two transmission modes of asymmetric dual link. Through FD-DMAC medium access, the neighbors of communication nodes can clearly know network transmission status, which will provide other opportunities of asymmetric IBFD dual communication and solve hidden node problem. Additionally, we leverage FD-DMAC to transmit received power information. This approach can assist communication nodes to adjust transmit powers and suppress INI. Finally, we give a theoretical analysis of network performance using a discrete-time Markov model. The numerical results show that FD-DMAC achieves a significant improvement over RTS/CTS in terms of throughput and delay.

A Fibonacci Posterorder Circulants (피보나치 후위순회 원형군)

  • Kim Yong-Seok
    • Proceedings of the Korea Information Processing Society Conference
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    • pp.743-746
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    • 2006
  • In this paper, we propose and analyze a new parallel computer topology, called the Fibonacci posterorder circulants. It connects ${\Large f}_x,\;n{\geq}2$ processing nodes, same the number of nodes used in a comparable Fibonacci cube. Yet its diameter is only ${\lfloor}\frac{n}{3}{\rfloor}$ almost one third that of the Fibonacci cube. Fibonacci cube is asymmetric, but it is a regular and symmetric static interconnection networks for large-scale, loosely coupled systems. It includes scalability and Fibonacci cube as a spanning subgraph.

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Verification of New Family for Cascade Multilevel Inverters with Reduction of Components

  • Banaei, M.R.;Salary, E.
    • Journal of Electrical Engineering and Technology
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    • v.6 no.2
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    • pp.245-254
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    • 2011
  • This paper presents a new group for multilevel converter that operates as symmetric and asymmetric state. The proposed multilevel converter generates DC voltage levels similar to other topologies with less number of semiconductor switches. It results in the reduction of the number of switches, losses, installation area, and converter cost. To verify the voltage injection capabilities of the proposed inverter, the proposed topology is used in dynamic voltage restorer (DVR) to restore load voltage. The operation and performance of the proposed multilevel converters are verified by simulation using SIMULINK/MATLAB and experimental results.

General Coupling Matrix Synthesis Method for Microwave Resonator Filters of Arbitrary Topology

  • Uhm, Man-Seok;Lee, Ju-Seop;Yom, In-Bok;Kim, Jeong-Phill
    • ETRI Journal
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    • v.28 no.2
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    • pp.223-226
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    • 2006
  • This letter presents a new approach to synthesize the resonator filters of an arbitrary topology. This method employs an optimization method based on the relation between the polynomial coefficients of the transfer function and those of the $S_{21}$ from the coupling matrix. Therefore, this new method can also be applied to self-equalized filters that were not considered in the conventional optimization methods. Two microwave filters, a symmetric 4-pole filter with four transmission zeros (TZs) and an asymmetric 8-pole filter with seven TZs, are synthesized using the present method for validation. Excellent agreement between the response of the transfer function and that of the synthesized $S_{21}$ from the coupling matrix is shown.

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Postorder Fibonacci Circulants (후위순회 피보나치 원형군)

  • Kim, Yong-Seok;Roo, Myung-Gi
    • The KIPS Transactions:PartA
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    • v.15A no.1
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    • pp.27-34
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    • 2008
  • In this paper, We propose a new parallel computer topology, called the Postorder Fibonacci Circulants and analyze its properties. It is compared with Fibonacci cubes, when its number of nodes is kept the same of comparable one. Its diameter is improved from n-2 to $[\frac{n}{3}]$ and its topology is changed from asymmetric to symmetric. It includes Fibonacci cube as a spanning graph.