• Title, Summary, Keyword: VLSI architecture

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A VLSI Architecture for the Real-Time 2-D Digital Signal Processing (실시간 2차원 디지털 신호처리를 위한 VLSI 구조)

  • 권희훈
    • Information and Communications Magazine
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    • v.9 no.9
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    • pp.72-85
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    • 1992
  • The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

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VLSI Architecture for Computer-Generated Hologram (컴퓨터 생성 홀로그램을 위한 VLSI 구조)

  • Seo, Young-Ho;Choi, Hyun-Jun;Kim, Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.7C
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    • pp.540-547
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    • 2008
  • In this paper, we proposed a new VLSI architecture which can generate computer-generated hologram (CGH) in real-time and implemented to hardware. The modified algorithm for high-performance CGH was introduced and re-analyzed (or designing hardware. from both numerical and visual analysis, the infernal number system of hardware was decided. CGH algorithm and precision analysis enabled to propose a new cell architecture for CGH. The operational sequence was analyzed with the architecture of CGH cell and the characteristics of the modified CGH algorithm, and finally the pipelined architecture and the operational timing were proposed.

On a Reduction of Pitch Searching Time by Separating the Speech Components in the CELP Vocoder (성분분리에 의한 CELP 보코더의 피치 검색시간 단축에 관한 연구)

  • Hyeon, Jin-Il;Byeon, Gyeong-Jin;Han, Gi-Cheon;Kim, Jong-Jae;Yu, Ha-Yeong;Kim, Jae-Seok;Kim, Dae-Sik;Bae, Myeong-Jin
    • The Journal of the Acoustical Society of Korea
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    • v.14 no.1E
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    • pp.22-29
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    • 1995
  • Code excited Linear Prediction(CELP) vocoder exhibits good performance at data rates below 4.8 kbps. The major drawback of CELP type coders is their large amount of computation. In this paper, we propose a new pitch searching method that preseves the quality of the CELP vodocer reducing computational complexity. The basic idea is that pregrasps preliminary pitches about signal and performs pitch search only about the preliminary pitches. Applying the proposed method to the CELP vocoder, we can reduce complexity about 90% in th pitch search.

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A Study on a VLSI Architecture for Reed-Solomon Decoder Based on the Berlekamp Algorithm (Berlekamp 알고리즘을 이용한 Reed-Solomon 복호기의 VLSI 구조에 관한 연구)

  • 김용환;정영모;이상욱
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.11
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    • pp.17-26
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    • 1993
  • In this paper, a VlSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provided both erasure and error correcting capability. In order to reduc the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed, and the overall architecture features parallel and pipelined structure, making a real time decoding possible. From the performance evaluation, it is concluded that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the rcursive architecture based on the Euclid algorithm.

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A VLSI Design for High-speed Data Processing of Differential Phase Detectors with Decision Feedback (결정 궤환 구조를 갖는 차동 위상 검출기의 고속 데이터 처리를 위한 VLSI 설계)

  • Kim, Chang-Gon;Jeong, Jeong-Hwa
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.74-86
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    • 2002
  • This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.

Deblocking Filter Based on Edge-Preserving Algorithm And an Efficient VLSI Architecture (경계선 보존 알고리즘 기반의 디블로킹 필터와 효율적인 VLSI 구조)

  • Vinh, Truong Quang;Kim, Ji-Hoon;Kim, Young-Chul
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.11C
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    • pp.662-672
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    • 2011
  • This paper presents a new edge-preserving algorithm and its VLSI architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-preserving maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is prototyped on FPGA Cyclone II, and then we estimated performance when the filter is synthesized on ANAM 0.25 ${\mu}m$ CMOS cell library using Synopsys Design Compiler. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details.

VLSI Architecture for Video Object Boundary Enhancement (비디오객체의 경계향상을 위한 VLSI 구조)

  • Kim, Jinsang-
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.11A
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    • pp.1098-1103
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    • 2005
  • The edge and contour information are very much appreciated by the human visual systems and are responsible for our perceptions and recognitions. Therefore, if edge information is integrated during extracting video objects, we can generate boundaries of oects closer to human visual systems for multimedia applications such as interaction between video objects, object-based coding, and representation. Most of object extraction methods are difficult to implement real-time systems due to their iterative and complex arithmetic operations. In this paper, we propose a VLSI architecture integrating edge information to extract video objects for precisely located object boundaries. The proposed architecture can be easily implemented into hardware due to simple arithmetic operations. Also, it can be applied to real-time object extraction for object-oriented multimedia applications.

Design and Implementation of Motion Estimation VLSI Processor using Block Matching Algorithm (완전탐색 블럭정합 알고리듬을 이용한 움직임 추정기의 VLSI 설계 및 구현)

  • 이용훈;권용무;박호근;류근장;김형곤;이문기
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.9
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    • pp.76-84
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    • 1994
  • This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.

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A VLSI architecture for the multi-dimensional digital filter (다차원 디지탈 필터의 VLSI 구조)

  • Jeong, Jae-Gil;Kim, Yong-Hoh
    • The Journal of Natural Sciences
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    • v.8 no.2
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    • pp.69-75
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    • 1996
  • This paper presents a VLSI architecture for the efficient implementation of the real time multi-dimensional digital filter. The computational primitive for the filter is obtained from the state space representation of the multi-dimensional general order filter. The computational primitive is used for the data path of the processor.

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