• Title, Summary, Keyword: cryptographic

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FPGA Implementation of a Cryptographic Accelerator for IPSec authentications

  • Lee, Kwang-Youb;Kwak, Jae-Chang
    • Proceedings of the IEEK Conference
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    • pp.948-950
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    • 2002
  • IPSec authentication provides support for data integrity and authentication of IP packets. Authentication is based on the use of a message authentication code(MAC). Hash function algorithm is used to produce MAC , which is referred to HMAC. In this paper, we propose a cryptographic accelerator using FPGA implementations. The accelator consists of a hash function mechanism based on MD5 algorithm, and a public-key generator based on a Elliptiv Curve algorithm with small scale of circuits. The accelator provides a messsage authentification as well as a digital signature. Implementation results show the proposed cryptographic accelerator can be applied to IPSec authentications.

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VLSI Design of AES Cryptographic Processor (AES 암호 프로세서의 VLSI 설계)

  • 정진욱;최병윤;서정욱
    • Proceedings of the IEEK Conference
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    • pp.285-288
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    • 2001
  • In this paper a design of cryptographic coprocessor which implements AES Rijndael algorithm is described. To achieve average throughput of 1 round per 5 clocks, subround pipelined scheme is applied. To apply the coprocessor to various applications, three key sizes such as 128, 192, 256 bits are supported. The cryptographic coprocessor is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology and consists of about 36, 000 gates. Its peak performance is about 512 Mbps encryption or decryption rate under 200 Mhz clock frequency and 128-bit key ECB mode(AES-128ECB).

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VLSI Design of Cryptographic Processor for SEED and Triple DES Encryption Algorithm (SEED 와 TDES 암호 알고리즘을 구현하는 암호 프로세서의 VLSI 설계)

  • 정진욱;최병윤
    • Proceedings of the IEEK Conference
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    • pp.169-172
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    • 2000
  • This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

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FPGA Implementation of RSA Public-Key Cryptographic Coprocessor for Restricted System

  • Kim, Mooseop;Park, Yongje;Kim, Howon
    • Proceedings of the IEEK Conference
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    • pp.1551-1554
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    • 2002
  • In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for smart card. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a 10240it RSA cryptographic processor based on proposed scheme in IESA system developed for smart card emulating system. As a result, it is shown that proposed architecture contributes to small area and reasonable speed for smart cards.

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Design of A Cryptographic Add-on Card Dedicated to SOHO VPN (SOHO VPN 시스템에 특화된 암호가속카드의 설계 및 구현)

  • Lee, Wan-Bok
    • Convergence Security Journal
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    • v.5 no.3
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    • pp.87-92
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    • 2005
  • The performance of a cryptographic module is the most important thing to achieve a high performance VPN system which realizes information security by encrypting and decrypting all the communicating data packets. However the cryptographic operations require much computation power and software cryptographic systems reveal bad performance. Thus, it is strongly recommended to develop a VPN system employing hardware component. This paper introduces a case study of developing a PCI add-on card which supports several block cipher algorithms such as DES, 3DES, AES, and SEED. The performance of them was measured by embedding the card in a commercial VPN system.

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A Study of Practical Field Application Cryptographic Module through Evaluation Derived by Connection Indicators (품질 연계지표 평가방법을 사용한 암호화 모듈 실무현장 적용체계 연구)

  • Noh, SiChoon;Na, SangYeob
    • Convergence Security Journal
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    • v.14 no.4
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    • pp.55-60
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    • 2014
  • In this study, we propose a cryptographic module quality evaluation system referenced by ISO/IEC 9000 quality system with Quality, Quality Factor, Quality Subfactor, Metric. Practical application process encryption algorithm based on the encryption algorithm to encrypt the pros and cons valuation of diagnosis, point selection algorithm, analysis, and quality items(quality factor), eliciting constraints derived, such as the cryptographic module design quality evaluation system is set to step 5. The five steps are examples of field-based diagnostic tool for cryptographic operations, the most essential work to be done in order to derive one will work. 2-Factor encryption module for connection between indicator items(quality factor) to identify and ensure the quality of the item the constraints of the environment are two kinds of cryptographic operations. This study is an encryption module and a practical field application system, it presents the standardized model. We have to meet the rapid changes in information technology. The environment, development and the encryption algorithm applied to model a wide variety of on-site development encryption will be able to expect the efficiency.

The cryptographic module design requirements of Flight Termination System for secure cryptogram delivery (안전한 보안명령 전달을 위한 비행종단시스템용 암호화 장치 설계 요구사항)

  • Hwang, Soosul;Kim, Myunghwan;Jung, Haeseung;Oh, Changyul;Ma, Keunsu
    • Journal of Satellite, Information and Communications
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    • v.10 no.3
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    • pp.114-120
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    • 2015
  • In this paper, we show the design requirements of the cryptographic module and its security algorithm designed to prevent the exposure of the command signal applied to Flight Termination System. The cryptographic module consists of two separate devices that are Command Insertion Device and Command Generation Device. The cryptographic module designed to meet the 3 principles(Confidentiality, Integrity and Availability) for the information security. AES-256 block encryption algorithm and SHA-256 Hash function were applied to the encrypted symmetric key encryption method. The proposed cryptographic module is expected to contribute to the security and reliability of the Flight Termination System for Space Launch Vehicle.

Loop Probe Design and Measurement of Electromagnetic Wave Signal for Contactless Cryptographic Analysis (비접촉 암호 분석용 루프 프로브 설계 및 전자파 신호 측정)

  • Choi, Jong-Kyun;Kim, Che-Young;Park, Jea-Hoon;Moon, Snag-Jae
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.10
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    • pp.1117-1125
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    • 2007
  • In this paper, a study has been performed on the design of small loop probe and analysis of induced electromagnetic wave signal from a smartcard for contactless cryptographic analysis. Probes for cryptographic analysis are different from conventional EM probes, because the purpose of proposed probe is to obtain the information for secret key analysis of cryptographic system. The waveform of induced voltage on probe must be very close to radiated waveform from IC chip on smartcard because electromagnetic attack makes an attempt to analyze the radiated waveform from smartcard. In order to obtain secret key information, we need to study about cryptographic analysis using electromagnetic waves, an approximate model of source, characteristic of probe for cryptographic analysis, measurement of electromagnetic waves and calibration of probes. We measured power consumption signal on a smartcard chip and electromagnetic wave signal using proposed probe and compared with two signals of EMA point of view. We verified experimently the suitability of the proposed small loop probe for contactless cryptographic analysis by applying ARIA algorithm.

Analysis of IoT Open-Platform Cryptographic Technology and Security Requirements (IoT 오픈 플랫폼 암호기술 현황 및 보안 요구사항 분석)

  • Choi, Jung-In;Oh, Yoon-Seok;Kim, Do-won;Choi, Eun Young;Seo, Seung-Hyun
    • KIPS Transactions on Computer and Communication Systems
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    • v.7 no.7
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    • pp.183-194
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    • 2018
  • With the rapid development of IoT(Internet of Things) technology, various convenient services such as smart home and smart city have been realized. However, IoT devices in unmanned environments are exposed to various security threats including eavesdropping and data forgery, information leakage due to unauthorized access. To build a secure IoT environment, it is necessary to use proper cryptographic technologies to IoT devices. But, it is impossible to apply the technologies applied in the existing IT environment, due to the limited resources of the IoT devices. In this paper, we survey the classification of IoT devices according to the performance and analyze the security requirements for IoT devices. Also we survey and analyze the use of cryptographic technologies in the current status of IoT open standard platform such as AllJoyn, oneM2M, IoTivity. Based on the research of cryptographic usage, we examine whether each platform satisfies security requirements. Each IoT open platform provides cryptographic technology for supporting security services such as confidentiality, integrity, authentication an authorization. However, resource constrained IoT devices such as blood pressure monitoring sensors are difficult to apply existing cryptographic techniques. Thus, it is necessary to study cryptographic technologies for power-limited and resource constrained IoT devices in unattended environments.