• Title, Summary, Keyword: ggNMOS

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AC Modeling of the ggNMOS ESD Protection Device

  • Choi, Jin-Young
    • ETRI Journal
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    • v.27 no.5
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    • pp.628-634
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    • 2005
  • From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.

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Design of SCR-Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

  • Jung, Jin Woo;Koo, Yong Seo
    • ETRI Journal
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    • v.37 no.1
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    • pp.97-106
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    • 2015
  • In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

A study on ESD Protection circuit based on 4H-SiC MOSFET (4H-SiC MOSFET기반 ESD보호회로에 관한 연구)

  • Seo, Jeong-Ju;Do, Kyoung-Il;Seo, Jeong-Ju;Kwon, Sang-Wook;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1202-1205
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    • 2018
  • In this paper, we proposed ggNMOS based on 4H-SiC material and analyzed its electrical characteristics. 4H-SiC is a wide band-gap meterial, which is superior in area contrast and high voltage characteristics to Si material, and is attracting attention in the power semiconductor field. The proposed device has high robustness and strong snapback characteristics. The process consisted of SiC process and electrical characteristics were analyzed by TLP measurement equipment.

New Thyristor Based ESD Protection Devices with High Holding Voltages for On-Chip ESD Protection Circuits

  • Hwang, Suen-Ki;Cheong, Ha-Young
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.12 no.2
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    • pp.150-154
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    • 2019
  • In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

Characteristics of Double Polarity Source-Grounded Gate-Extended Drain NMOS Device for Electro-Static Discharge Protection of High Voltage Operating Microchip (마이크로 칩의 정전기 방지를 위한 DPS-GG-EDNMOS 소자의 특성)

  • Seo, Yong-Jin;Kim, Kil-Ho;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.97-98
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    • 2006
  • High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

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High Current Behavior and Double Snapback Mechanism Analysis of Gate Grounded Extended Drain NMOS Device for ESD Protection Device Application of DDIC Chip (DDIC 칩의 정전기 보호 소자로 적용되는 GG_EDNMOS 소자의 고전류 특성 및 더블 스냅백 메커니즘 분석)

  • Yang, Jun-Won;Kim, Hyung-Ho;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.8 no.2
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    • pp.36-43
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    • 2013
  • In this study, the high current behaviors and double snapback mechanism of gate grounded_extended drain n-type MOSFET(GG_EDNMOS) device were analyzed in order to realize the robust electrostatic discharge(ESD) protection performances of high voltage operating display driver IC(DDIC) chips. Both the transmission line pulse(TLP) data and the thermal incorporated 2-dimensional simulation analysis as a function of ion implant conditions demonstrate a characteristic double snapback phenomenon after triggering of bipolar junction transistor(BJT) operation. Also, the background carrier density is proven to be a critical factor to affect the high current behavior of the GG_EDNMOS devices.

A Design of Peak Current-mode DC-DC Buck Converter with ESD Protection Devices (ESD 보호 소자를 탑재한 Peak Current-mode DC-DC Buck Converter)

  • Park, Jun-Soo;Song, Bo-Bae;Yoo, Dae-Yeol;Lee, Joo-Young;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.17 no.1
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    • pp.77-82
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    • 2013
  • In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

A Comparative Study on the Removals of 1-Naphthol by Natural Manganese Oxides and Birnessite (천연망간산화물과 버네사이트에 의한 1-Naphthol의 제거 특성 비교)

  • Lee, Doo-Hee;Harn, Yoon-I;Kang, Ki-Hoon;Shin, Hyun-Sang
    • Journal of Korean Society of Environmental Engineers
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    • v.31 no.4
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    • pp.278-286
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    • 2009
  • In this study, four natural Mn oxides ($NMO_1-NMO_4$) was characterized using x-ray diffraction, scanning electron microscopy, and their removal efficiency for 1-naphthol (1-NP) in aqueous phase, using batch reactor, was investigated. The results were compared with one another and a synthetic manganese oxide, birnessite. The NMOs have a various Mn minerals including pyrolusite (${\beta}-MnO_2$), cryptomeltane (${\alpha}-MnO_2$) as well as birnessite (${\delta}-MnO_2$) depending on their sources, which results in different removal efficiencies (removals, kinetics) and reaction types (sorption or oxidative-transformation). The comparative study showed that $NMO_1$ (electrolytic Mn oxide) have a higher removal efficiency for 1-NP via oxidative-transformation compared to birnessite. The 1-NP removals by NMOs were followed by pseudo-first order reaction, and the surface area-normalized specific rate constants ($K_{surf},\;L/m^2$ min) determined were in order of $NMO_1(3.31{\times}10^{-3})$>${\delta}-MnO_2(1.48{\times}10^{-3}){\fallingdotseq}NMO_3(1.46{\times}10^{-3})$>$NMO_2(0.83{\times}10^{-3})$>$NMO_4(0.67{\times}10^{-3})$. From the solvent extraction experiments with the Mn oxide precipitates after reaction, it was observed that the oxidative-transformation rates of 1-NP were in order of $NMO_1{\fallingdotseq}{\delta}-MnO_2$>$NMO_3$>$NMO_4{\gg}NMO_2$ and the analysis of HPLC chromatogram and UV-Vis. absorption ratios ($A_{2/4}$, $A_{2/6}$) on the supernatant confirmed that the reaction products were oligomers formed by oxidative-coupling reaction. Results from this study proved that natural Mn oxide (except $NMO_2$) used in this experiment can be effectively applied for the removal of naphthols in aqueous phase, and the removal efficiencies are depending on the surface characters of the Mn oxides.

A Design of Current-mode Buck-Boost Converter using Multiple Switch with ESD Protection Devices (ESD 보호 소자를 탑재한 다중 스위치 전류모드 Buck-Boost Converter)

  • Kim, Kyung-Hwan;Lee, Byung-Suk;Kim, Dong-Su;Park, Won-Suk;Jung, Jun-Mo
    • Journal of IKEEE
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    • v.15 no.4
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    • pp.330-338
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    • 2011
  • In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).