• Title, Summary, Keyword: hardware architecture

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A study on Hardware Redundancy Architecture of Fault-Tolerant System (결함허용 시스템의 하드웨어 여분구조에 대한 연구)

  • shin Ducko;Lee Jong-woo;Lee Jae-ho;Lee Key-seo
    • Proceedings of the KSR Conference
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    • pp.450-455
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    • 2003
  • This paper is to discuss the hardware redundancy architecture of fault-tolerance system with using redundancy. Each architecture will be studied to implement fault-tolerance in classifying hardware redundancy architecture as passive, active and hybrid hardware redundancy. Therefore Fault-Masking and Fault-Detecting Techniques in each redundancy architecture is studied.

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Hardware architecture of a wavelet based multiple line addressing driving system for passive matrix displays

  • Lam, San;Smet, Herbert De
    • 한국정보디스플레이학회:학술대회논문집
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    • pp.802-805
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    • 2007
  • A hardware architecture is presented of a wavelet based multiple line addressing driving scheme for passive matrix displays using the FPGA (Field Programmable Gate Arrays), which will be integrated in the scalable video coding $architecture^{[1]}$. The incoming compressed video data stream will then directly be transformed to the required column voltages by the hardware architecture without the need of employing the video decompression.

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An Efficient Hardware Architecture of Coordinate Transformation for Panorama Unrolling of Catadioptric Omnidirectional Images

  • Lee, Seung-Ho
    • Journal of IKEEE
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    • v.15 no.1
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    • pp.10-14
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    • 2011
  • In this paper, we present an efficient hardware architecture of unrolling image mapper of catadioptric omnidirectional imaging systems. The catadioptric omnidirectional imaging systems generate images of 360 degrees of view and need to be transformed into panorama images in rectangular coordinate. In most application, it has to perform the panorama unrolling in real-time and at low-cost, especially for high-resolution images. The proposed hardware architecture adopts a software/hardware cooperative structure and employs several optimization schemes using look-up-table(LUT) of coordinate conversion. To avoid the on-line division operation caused by the coordinate transformation algorithm, the proposed architecture has the LUT which has pre-computed division factors. And then, the amount of memory used by the LUT is reduced to 1/4 by using symmetrical characteristic compared with the conventional architecture. Experimental results show that the proposed hardware architecture achieves an effective real-time performance and lower implementation cost, and it can be applied to other kinds of catadioptric omnidirectional imaging systems.

A hardware implementation of neural network with modified HANNIBAL architecture (수정된 하니발 구조를 이용한 신경회로망의 하드웨어 구현)

  • 이범엽;정덕진
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.45 no.3
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    • pp.444-450
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    • 1996
  • A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). refs., figs., tabs.

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Design of Reconfigurable Hardware for FIR Filters (재구성 가능한 FIR 필터 하드웨어 구조 설계)

  • Dong, Sung-Soo;Lee, Chong-Ho
    • Proceedings of the KIEE Conference
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    • pp.309-311
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    • 2005
  • In general, for specific applications, customized hardware showed better performance than general processor in terms of processing time and power consumption. However, customized hardware systems have lacks of flexibility in nature and it leads the difficulties for debugging and architecture level revision for performance enhancement. To solve this problem, reconfigurable hardware is developed. Proposed reconfigurable hardware architecture for FIR filter system can easily change the architecture of filter blocks including filter tap size and their signal path. Proposed FIR filter architecture was implemented on FPGA using several MUXs and registers and it showed the reconfigurablility and reusability in several examples.

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Parallel 2D-DWT Hardware Architecture for Image Compression Using the Lifting Scheme (이미지 압축을 위한 Lifting Scheme을 이용한 병렬 2D-DWT 하드웨어 구조)

  • Kim, Jong-Woog;Chong, Jong-Wha
    • Journal of IKEEE
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    • v.6 no.1
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    • pp.80-86
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    • 2002
  • This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

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Gradient Magnitude Hardware Architecture based on Hardware Folding Design Method for Low Power Image Feature Extraction Hardware Design (저전력 영상 특징 추출 하드웨어 설계를 위한 하드웨어 폴딩 기법 기반 그라디언트 매그니튜드 연산기 구조)

  • Kim, WooSuk;Lee, Juseong;An, Ho-Myoung
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.10 no.2
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    • pp.141-146
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    • 2017
  • In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

Low Complexity Gradient Magnitude Calculator Hardware Architecture Using Characteristic Analysis of Projection Vector and Hardware Resource Sharing (정사영 벡터의 특징 분석 및 하드웨어 자원 공유기법을 이용한 저면적 Gradient Magnitude 연산 하드웨어 구현)

  • Kim, WooSuk;Lee, Juseong;An, Ho-Myoung
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.9 no.4
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    • pp.414-418
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    • 2016
  • In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

A Study on Hardware Implementation of a VSB Equalization System (VSB 등화시스템의 하드웨어 구현방법에 관한 연구)

  • 채승수;박래홍
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.10
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    • pp.1314-1325
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    • 1995
  • In this paper, we describe hardware implementation of VSB (Vestigial SideBand) mo-dulation equalization systems for HDTV (High Definition TeleVision). By modifying an adaptive equalization algorithm, we propose a hardware architecture with a low hardware cost and the performance close to floating-point operations. We also employ the pipeline concept to reduce the hardware cost. The effectiveness of the proposed hardware architecture is de- monstrated through computer simulation and the optimization result of VHDL circuit descriptions.

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VLSI Architecture for Computer-Generated Hologram (컴퓨터 생성 홀로그램을 위한 VLSI 구조)

  • Seo, Young-Ho;Choi, Hyun-Jun;Kim, Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.7C
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    • pp.540-547
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    • 2008
  • In this paper, we proposed a new VLSI architecture which can generate computer-generated hologram (CGH) in real-time and implemented to hardware. The modified algorithm for high-performance CGH was introduced and re-analyzed (or designing hardware. from both numerical and visual analysis, the infernal number system of hardware was decided. CGH algorithm and precision analysis enabled to propose a new cell architecture for CGH. The operational sequence was analyzed with the architecture of CGH cell and the characteristics of the modified CGH algorithm, and finally the pipelined architecture and the operational timing were proposed.