• Title, Summary, Keyword: hardware performance counter

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On the Conceptual Design of the SIMD Vector Machine Attachable to SISD Machine (SISD 머신에 부착 가능한 SIMD 벡터 머신의 개념적 설계)

  • Cho Young-Il;Ko Young-Woong
    • The KIPS Transactions:PartA
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    • v.12A no.3
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    • pp.263-272
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    • 2005
  • The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).

Digital Correlator Design for GPS/GLONASS Receiver (GPS/GLONASS 수신기용 디지털 상관기 설계)

  • 조득재;최일홍;박찬식;이상정
    • 제어로봇시스템학회:학술대회논문집
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    • pp.275-275
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    • 2000
  • This paper designs a digital correlator for the integrated GPS/GLONASS receiver consisting of DCO, carrier cycle counter, code generator, code phase counter, mixer, epoch counter, accumulator. It is designed using Verilog-HDL(Verilog-Hardware Description Language) and synthesized using EDA(Electronic Design Automation) tools. The performance of the designed digital correlator is verified by the functional simulation and real satellite tracking experiments.

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Performance Improvement of Smart Counter for Uneven Small Grain (지능형 미소비균일체 계수기의 성능개선)

  • Cho, Si-Hyeong;Park, Chan-Won
    • Journal of Industrial Technology
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    • v.29 no.B
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    • pp.127-131
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    • 2009
  • This paper presents the development of smart counting system that is proper for grains with uneven unit weight or shape. This device can detect the small differences of a light beam and count the pulse from wave shape control, when the grain is going on the light screen, which is made by the light beam screen sensor. It can, different from the former conventional device, distinct the uneven grains for counting detect, by using the dedicated hardware and the software algorithm of the light sensor.

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Development of Efficient Dynamic Bandwidth Allocation Algorithm for XGPON

  • Han, Man Soo;Yoo, Hark;Lee, Dong Soo
    • ETRI Journal
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    • v.35 no.1
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    • pp.18-26
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    • 2013
  • This paper proposes an efficient bandwidth utilization (EBU) algorithm that utilizes the unused bandwidth in dynamic bandwidth allocation (DBA) of a 10-gigabit-capable passive optical network (XGPON). In EBU, an available byte counter of a queue can be negative and the unused remainder of an available byte counter can be utilized by the other queues. In addition, EBU uses a novel polling scheme to collect the requests of queues as soon as possible. We show through analysis and simulations that EBU improves performance compared to that achieved with existing methods. In addition, we describe the hardware implementation of EBU. Finally we show the test results of the hardware implementation of EBU.

Hardware Implementation of an Intelligent Controller with a DSP and an FPGA for Nonlinear Systems (DSP와 FPGA를 이용한 지능 제어기의 하드웨어 구현)

  • 김성수
    • Journal of Institute of Control, Robotics and Systems
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    • v.10 no.10
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    • pp.922-929
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    • 2004
  • In this paper, we develop control hardware such as an FPGA based general purposed intelligent controller with a DSP board to solve nonlinear system control problems. PID control algorithms are implemented in an FPGA and neural network control algorithms are implemented in a BSP board. An FPGA was programmed with VHDL to achieve high performance and flexibility. The additional hardware such as an encoder counter and a PWM generator can be implemented in a single FPGA device. As a result, the noise and power dissipation problems can be minimized and the cost effectiveness can be achieved. To show the performance of the developed controller, it was tested fur nonlinear systems such as a robot hand and an inverted pendulum.

AndroScope: An Insightful Performance Analyzer for All Software Layers of the Android-Based Systems

  • Cho, Myeongjin;Lee, Ho Jin;Kim, Minseong;Kim, Seon Wook
    • ETRI Journal
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    • v.35 no.2
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    • pp.259-269
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    • 2013
  • Android has become the most popular platform for mobile devices. However, Android still has critical performance issues, such as "application not responding" errors and hiccups resulting from garbage collection. Many phone vendors have tried to resolve the problems by characterizing and improving the performance. However, there are few insightful performance analysis tools for the Android-based systems. This paper presents AndroScope, which is a performance analysis tool for both the Android platform (Dalvik virtual machine, core libraries, Android libraries, and even Linux kernels) and its applications. To the best of our knowledge, this is the first tool to collect and analyze performance data from all the software layers of the Android-based systems. AndroScope offers a trace mechanism to collect such deep and wide performance data as hardware performance counters, time, and memory usage. In addition, the tool includes TraceBridge, which is a middleware for the fast handling of mass logs. Moreover, AndroScope offers an integrated graphical user interface with the Android software development kit to display a great volume of the detailed performance data.

Implementation of an Intelligent Controller with a DSP and an FPGA for Nonlinear Systems

  • Kim, Sung-Su;Jung, Seul
    • 제어로봇시스템학회:학술대회논문집
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    • pp.575-580
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    • 2003
  • In this paper, we develop a control hardware such as an FPGA based general purpose controller with a DSP board to solve nonlinear control problems. PID control algorithms are implemented in an FPGA and neural network control algorithms are implemented in a DSP board. PID controllers implemented on an FPGA was designed by using VHDL to achieve high performance and flexibility. By using high capacity of an FPGA, the additional hardware such as an encoder counter and a PWM generator, can be implemented in a single FPGA device. As a result, the noise and power dissipation problems can be minimized and the cost effectiveness can be achieved. In order to show the performance of the developed controller, it was tested for controlling nonlinear systems such as an inverted pendulum.

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Efficient FPGA Implementation of AES-CCM for IEEE 1609.2 Vehicle Communications Security

  • Jeong, Chanbok;Kim, Youngmin
    • IEIE Transactions on Smart Processing and Computing
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    • v.6 no.2
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    • pp.133-139
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    • 2017
  • Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

A study on the design of the A-D converter for analog rebalance loop in INS (관성측정장치의 아날로그 재평형 루프에 따르는 A-D 변환기의 설계에 관한 연구)

  • 안영석;김종웅;이의행
    • 제어로봇시스템학회:학술대회논문집
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    • pp.522-527
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    • 1987
  • This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

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Counting detection for a small grains by using light screen sensing method ( Hardware ) (광막센싱방법을 이용한 미소물체의 계수검출 (하드웨어))

  • Cho, Si-Hyeong;Park, Chan-Won
    • Journal of Industrial Technology
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    • v.27 no.B
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    • pp.103-107
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    • 2007
  • In this paper, the light screen sensing system is introduced and testified to detect small grains such as seeds or electronic chips of uneven sized. Two modules composed of transmitter-receiver sensor array and microprocessor-based sensor signal processing system are developed to realize the proposed system. Experimental results showed that the sensing signal was relatively clear and its counting performance was very stable.

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