• Title, Summary, Keyword: holding voltage

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The novel SCR-based ESD Protection Device with High Holding Voltage (높은 홀딩전압을 갖는 사이리스터 기반 새로운 구조의 ESD 보호소자)

  • Won, Jong-Il;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.13 no.1
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    • pp.87-93
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    • 2009
  • The paper introduces a silicon controlled rectifier (SCR)-based device with high holding voltage for ESD power clamp. The holding voltage can be increased by extending a p+ cathode to the first n-well and adding second n-well wrapping around n+ cathode. The increase of the holding voltage above the supply voltage enables latch-up immune normal operation. In this study, the proposed device has been simulated using synopsys TCAD simulator for electrical characteristic, temperature characteristic, and ESD robustness. In the simulation result, the proposed device has holding voltage of 3.6V and trigger voltage of 10.5V. And it is confirmed that the device could have holding voltage of above 4V with the size variation of extended p+ cathode and additional n-well.

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New Thyristor Based ESD Protection Devices with High Holding Voltages for On-Chip ESD Protection Circuits

  • Hwang, Suen-Ki;Cheong, Ha-Young
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.12 no.2
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    • pp.150-154
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    • 2019
  • In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

Electrical Characteristics and Thermal Reliability of Stacked-SCRs ESD Protection Device for High Voltage Applications

  • Koo, Yong Seo;Kim, Dong Su;Eo, Jin Woo
    • Journal of Power Electronics
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    • v.12 no.6
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    • pp.947-953
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    • 2012
  • The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.18um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated.

Voltage Holding Ratio of a Homogeneously-Aligned Liquid-Crystal Cell

  • Lin, Yu-Ting;Lin, Yu-Jiun;Lee, Wei
    • 한국정보디스플레이학회:학술대회논문집
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    • pp.17-19
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    • 2009
  • The voltage and frequency dependence of voltage holding ratio (VHR) in a homogeneously-aligned liquid-crystal (LC) cell is studied in this paper. The discharge curves with different scan frequencies are obtained and the saturation phenomenon of VHR is observed under specific amplitudes of driving voltage. Our results suggest a reasonable concept to improve the VHR in LC displays without increasing the frame rate.

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The novel SCR-based ESD Protection Circuit with High Holding Voltage Applied for Power Clamp (파워 클램프용 높은 홀딩전압을 갖는 사이리스터 기반 새로운 구조의 ESD 보호회로)

  • Lee, Byung-Seok;Kim, Jong-Min;Byeon, Joong-Hyeok;Park, Won-Suk;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.17 no.2
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    • pp.208-213
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    • 2013
  • In this paper, we proposed the novel SCR-based ESD protection circuit with high holding voltage for power clamp. In order to increase the holding voltage, the floating p+ and n+ to n-well and p-well, respectively, in the conventional SCR. The resulting increase of the holding voltage of the our proposed ESD circuit enables the high latch-up immunity. The electrical characteristics including ESD robustness of the proposed ESD circuit have been simulated using Synopsys TCAD simulator. According to the simulation result, the proposed device has higher holding voltage of 4.98 V than that of the conventional SCR protection circuit. Moreover, it is confirmed that the device could have the holding voltage of maximum 13.26 V with the size variation of floated diffusion area.

Highly Robust AHHVSCR-Based ESD Protection Circuit

  • Song, Bo Bae;Koo, Yong Seo
    • ETRI Journal
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    • v.38 no.2
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    • pp.272-279
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    • 2016
  • In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

A Study on SCR-Based ESD Protection Device with Improved Robustness Using Stack Technology (Stack 기술을 이용한 향상된 감내 특성을 갖는 SCR 기반 ESD 보호 소자에 관한 연구)

  • Kwak, Jae-Chang
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.1015-1019
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    • 2019
  • In this paper, a new ESD protection device is proposed to improve the trigger voltage and robustness. The HHVSCR and the proposed device were compared to verify the trigger voltage, the holding voltage and the robustness. The gate length was modified to verify the electrical characteristics. The trigger voltage, the holding voltage and the robustness were certified by comparing the proposed device and the stacking structure.

The SCR-based ESD Protection Circuit with High Latch-up Immunity for Power Clamp (파워 클램프용 래치-업 면역 특성을 갖는 SCR 기반 ESD 보호회로)

  • Choi, Yong-Nam;Han, Jung-Woo;Nam, Jong-Ho;Kwak, Jae-Chang;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.18 no.1
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    • pp.25-30
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    • 2014
  • In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

The Design of SCR-based Whole-Chip ESD Protection with Dual-Direction and High Holding Voltage (양 방향성과 높은 홀딩전압을 갖는 사이리스터 기반 Whole-Chip ESD 보호회로)

  • Song, Bo-Bae;Han, Jung-Woo;Nam, Jong-Ho;Choi, Yong-Nam;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.378-384
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    • 2013
  • We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

Study on the SCR-based ESD Protection Circuit Using the Segmentation Layout Technique with High Holding Voltage (높은 홀딩 전압을 갖는 세그먼트 레이아웃 기법을 이용한 SCR 기반 ESD 보호회로에 관한 연구)

  • Park, Jun-Geol;Do, Kyoung-Il;Chae, Hee-Guk;Seo, Jeong-Yun;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.21 no.1
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    • pp.7-12
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    • 2017
  • This paper proposed the ESD protection circuit for the high-voltage applications with latch-up immunity and high area efficiency. The proposed circuit has high holding voltage compared to the conventional SCR by inserting the floating regions and applying the segmentation layout. It has the area efficiency is more higher due to the segmentation layout. The proposed circuit has the higher holding voltage of the 21.67V than the 3.39V of the conventional SCR. The electrical characteristics of the proposed circuit was investigated by TCAD simulator, and was proved through the fabrication by using the 0.18 BCD process.