• Title, Summary, Keyword: hot carrier effects

검색결과 63건 처리시간 0.049초

Hot Carrier 현상에 의한 Bulk DTMOS의 RF성능 저하 (The RF performance degradation in Bulk DTMOS due to Hot Carrier effect)

  • 박장우;이병진;유종근;박종태
    • 대한전자공학회논문지SD
    • /
    • v.42 no.2
    • /
    • pp.9-14
    • /
    • 2005
  • 본 논문에서는bulk dynamic threshold voltage MOSFET(B-DTMOS)와 bulk MOSFET(B-MOS)에서 hot carrier 현상으로 인한 RF 성능 저하를 비교하였다. Normal 및 moderate 모드에서 B-DTMOS의 차단주파수 및 최소잡음지수의 열화가 B-MOS 소자 보다 심하지 않음을 알 수 있었다. 실험 견과로부터 hot carrier에 의한 RF 성능 저하가 DC 특성 열화 보다 심함을 알 수 있었다. 그리고 처음으로 hot carrier 현상으로 인한 B-DTMOS 소자의 RF 전력 특성 저하를 측정하였다.

Electrical instabilities in p-channel polysilicon TFTs: role of hot carrier and self-heating effects

  • Fortunato, G.;Gaucci, P.;Mariucci, L.;Pecora, A.;Valletta, A.
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • /
    • pp.1065-1070
    • /
    • 2007
  • The effects of hot carriers and self-heating on the electrical stability of p-channel TFTs have been analysed combining experimental data and numerical simulations. While hot carrier effects were shown not to induce appreciable degradation, self-heating related instability was found to more seriously affect the device characteristics. New models have been developed to explain the reported results.

  • PDF

p-채널 Poly-Si TFT s 소자의 Hot-Carrier 효과에 관한 연구 (A Study on the Hot-Carrier Effects of p-Channel Poly-Si TFT s)

  • 진교원;박태성;백희원;이진민;조봉희;김영호
    • 한국전기전자재료학회논문지
    • /
    • v.11 no.9
    • /
    • pp.683-686
    • /
    • 1998
  • Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

  • PDF

LDD 공정 조건에 따른 편치쓰루 및 핫 캐리어 효과에 관한 연구 (A Study on Punchthrough and Hot-carrier Effects as LDD Process Parameters)

  • 안태현;김남훈;김창일;서용진;장의구
    • 대한전기학회:학술대회논문집
    • /
    • /
    • pp.1367-1369
    • /
    • 1998
  • To achieve the ULSI goals of higher density, greater performance and operation speed have been scaled down. However, the reduction of channel length cause undesirable problems such as drop of punchthrough voltage, hot-carrier degradation and high leakage current, etc.. It is shown that the device characteristics depend on process parameters. In this Paper, we catched hold of trends of hot-carrier effects and punchthrough voltages due to variation of some process parameters such as LDD doses(P), spacer lengths, channel doses($BF_2$) and $V_T$ adjusting channel implantation energies using design trend curve (DTC). As the LDD and channel doses increased, hot-carrier phenomena became more severe, and punchthrough voltage was decreased. It were represented that punchthrough and hot carrier effects were critically depend on LDD and channel doses.

  • PDF

p-채널 po1y-Si TFT 소자의 Hot-Carrier효과에 관한 연구 (A Study on the Hot-Carrier Effects of p-channel poly-Si TFT)

  • 진교원;박태성;이제혁;백희원;변문기;김영호
    • 한국전기전자재료학회:학술대회논문집
    • /
    • /
    • pp.266-269
    • /
    • 1997
  • Hot carrier effects as a function of bias stress time and bias stress conditions were syste-matica1ly investigated in p-channel po1y-Si TFT's fabricated on the quartz substrate. The device degradation was observed for the negative bias stress. After positive bias stressing, Improvement of electrical characteristic except for subthreshold slope was observed. It was found that these results were related to the hot carrier injection into the gate oxide and interface states at the poly-Si/SiO$_2$interface rather than defects states generation under bias stress.

  • PDF

Hot carrier 현상에 의한 CMOS 차동 증폭기의 성능 저하 (The performance degradation of CMOS differential amplifiers due to hot carrier effects)

  • 박현진;유종근;정운달;박종태
    • 전자공학회논문지D
    • /
    • v.34D no.7
    • /
    • pp.23-29
    • /
    • 1997
  • The performance degradation of CMOS differential amplifiers due to hot carrier effect has been measured and analyzed. Two-state CMOS amplifiers whose input transistors are PMOSFETs were designed and fabriacted using the ISRC CMOS 1.5.mu.m process. It was observed after the amplifier was hot-carrier stressed that the small-signal voltage gain and the input offset voltage increased and the phase margin decreased. The performance variation results from the increase of the transconductances and gate capacitances of the PMOSFETs used as input transistors in the differential input stage and the output stage and also resulted from the decrease of their output conductances. After long-term stress, the amplifier became unstable. The reason might be that its phase margin was reduced due to hot carrier effect.

  • PDF

Sub-micron 규모의 메몰 채널(buried-channel)P-MOSFETs에서의 핫-캐리어 현상 (Hot-carrier effects in sub-micron scaled buried-channel P-MOSFETs)

  • 정윤호;김종환;노병규;오환술;조용범
    • 전자공학회논문지A
    • /
    • v.33A no.10
    • /
    • pp.130-138
    • /
    • 1996
  • The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

  • PDF

산화막 및 재산화질화산화막의 MOS 캐패시터와 MOSFET의 신뢰성 (Reliability of MOS Capacitors and MOSFET's with Oxide and Reoxidized-Nitrided-Oxide as Gate Insulators)

  • 노태문;이경수;유병곤;남기수
    • 전자공학회논문지A
    • /
    • v.30A no.11
    • /
    • pp.105-112
    • /
    • 1993
  • Oxide and reoxidized-nitrided-oxide were formed by furnace oxidation and rapid thermal processing (RTP). MOS capacitor and n-MOSFET's with those films as gate insulators were fabricated. The electrical characteristics of insulators were evaluated by current-voltage, high-frequency capacitance-voltage (C-V), and time-dependent dielectrical breakdown (TDDB) measurements. The hot carrier effects of MOSFET's were also investigated. Time-dependent dielectrical breakdown (TDDB) characteristics show that the life time of reoxidized-nitrided-oxide films is about 3 times longer than that of oxides. Hot carrier effects reveal that the life time of MOSFET's with reoxidized-nitrided-oxides is about 3 times longer than that of MOSFET's with oxides. Therefore, it is found that the reliability of dielectric films estimated by the hot carrier effects of MOSFET's is consistent with that of dielectric films from TDDB method.

  • PDF

Deep submicrometer PMOSFET의 hot carrier 현상과 소자 노쇠화 (Hot carrier effects and device degradation in deep submicrometer PMOSFET)

  • 장성준;김용택;유종근;박종태;박병국;이종덕
    • 전자공학회논문지A
    • /
    • v.33A no.4
    • /
    • pp.129-135
    • /
    • 1996
  • In this paper, the hot carrier effect and device degradation of deep submicrometer SC-PMOSFETs have been measured and characterized. It has been shown that the substrate current of a 0.15$\mu$m PMOSFET increases with increasing of impact ionization rate, and the impact ionization rate is a function of the gate length and gate bias voltage. Correlation between gate current and substrate current is investigated within the general framework of the lucky-electron. It is found that the impact ionization rate increases, but the device degradation is not serious with decreasing effective channel length. SCIHE is suggested as the possible phusical mechanism for enhanced impact ionization rate and gate current reduction. Considering the hot carrier induced device degradation, it has been found that the maximum supply voltage is about -2.6V for 0.15$\mu$m PMOSFET.

  • PDF

Hot-Carrier 현상에 의한 Folded-Cascode CMOS OP-Amp의 성능 저하 (The performance degradation of a folded-cascode CMOS op-amp due to hot-carrier effects)

  • 김현중;유종근;정운달;박종태
    • 전자공학회논문지D
    • /
    • v.34D no.12
    • /
    • pp.39-45
    • /
    • 1997
  • This study presents the first experimental data for the impact of hot-carrier degradtion on the performance of CMOS folded-cascode op-amps. A folded-cascode op-amp which has an NMOS input pair has been designed and fabricated using a 0.8.mu.m single-poly, double-metal CMOS process. After high voltage stress, the degradtion of perfomrance parameters such as open-metal CMOS process. After high voltage stress, the degradation of performance parameters such as open-loop voltage gain, unity-gain frequency and phase margin has been analized and physically explaniend in terms of hot carrier degradation.

  • PDF