• Title, Summary, Keyword: information architecure

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Analyses of Security Architecture for a Virtual Heterogeneous Machine (가상 이종시스템간의 보안 구조 분석)

  • Kim, Jung-Tae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.2
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    • pp.791-794
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    • 2005
  • In this paper, we describe security for a virtual heterogeneous machine. Our security architecure is based on separation of services into for distinct system support for domains, where available. We have chosen to use emergong public key technology as an interim solution to provide domain seperation. Th proposed architecture has been analysed in numerically.

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Design and Implementation of UAV System for Autonomous Tracking

  • Cho, Eunsung;Ryoo, Intae
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.2
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    • pp.829-842
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    • 2018
  • Unmanned Aerial Vehicle (UAV) is diversely utilized in our lives such as daily hobbies, specialized video image taking and disaster prevention activities. New ways of UAV application have been explored recently such as UAV-based delivery. However, most UAV systems are being utilized in a passive form such as real-time video image monitoring, filmed image ground analysis and storage. For more proactive UAV utilization, there should be higher-performance UAV and large-capacity memory than those presently utilized. Against this backdrop, this study described the general matters on proactive software platform and high-performance UAV hardware for real-time target tracking; implemented research on its design and implementation, and described its implementation method. Moreover, in its established platform, this study measured and analyzed the core-specific CPU consumption.

Design and Implemention of Multimedia Integrated Processing Unit for Computer-Nased Video Conference (컴퓨터 영상회의를 위한 멀티미디어 통합처리장치의 설계 및 구현)

  • 김현기;홍재근
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.3
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    • pp.59-68
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    • 1998
  • This paper propose a hardware architecure of multimediasysgem for integrated processing of the multimedia data such as audio and video, and describes on the design and implementation of multimedia integrated processing Unit. The unit comprises most commonly needed multimedia processing function for computer-based video conference: audio-visual datacapture, playback, compression, decompression as well as interleaving/disinterleaving of compressed audio-visual data. The proposed architecture minimizes the CPU overhead that might be caused by multimedia data processing and assures the fluent data flow among system components. Also, this unit is tested and analyzed under the computer-based video conference to confirm the multimedia unit of proposed architecture using communication protocol and application software through Ethernet and FDDI (Fiber Distributed Data Interface) networks.

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A Study on the Design of the Technology Reference Model Based on Technologies of Interoperability in Digital Libraries (디지털 도서관 상호운영성 기술요소에 기반한 기술 참조 모델 설계에 관한 연구)

  • Kim, Seong-Hee;Lee, Jeong-Soo
    • Journal of the Korean Society for information Management
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    • v.24 no.4
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    • pp.239-254
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    • 2007
  • In order to solve the problems of the digital library's Interoperability and integrated management, we analyzed core technologies for interoperability in digital library in terms of information creation, organization, service. And then we proposed information technology reference model that is composed of 7 scopes. The proposed scope included 1)Metadata Management, 2)Library Services, 3)Service Integration 4)Service Management, 5)Open Interface, 6)Network, 7)Architecture. Those results can be used as a framework for developing interoperable digital library system.

A Study on Utilization of Unmanned Aerial Vehicle for Automated Inspection for Building Occupancy Authorization (건축물 사용승인 제도의 현장조사 자동화를 위한 UAV활용방안 연구)

  • Lee, Seung Hyeon;Ryu, Jung Rim;Choo, Seung Yeon
    • Korean Journal of Computational Design and Engineering
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    • v.22 no.1
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    • pp.44-58
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    • 2017
  • The inspection for building occupancy authorization has lacked objectivity due to manual measurement methods. This is why connivance of the illegal buildings has been rampant, which has led to so many incidents. Consequently, this law has lost its intent to protect people's lives and property. In this study, for the purpose of improvement of this law, the research was conducted by the utilization of unmanned aerial vehicle for automated inspection for building occupancy authorization. Theoretical considerations about building occupancy authorization and the trend of UAV technology were accomplished. Secondly, a series of reverse engineering was conducted including digital photography, network RTK-VRS surveying and post-processing data. Thirdly, the resultant spatial information was used for building occupancy inspection authorization in a BIM platform and the effectiveness and applicability of UAV-based inspection was analyzed. As a result, methodology for UAV-based automated building occupancy inspection authorization was derived. And it was found that eleven items would be possible to be automated among thirty total items for building occupancy authorization. Also it was found that UAV-based automated inspection could be valid in inspecting building occupancy authorization due to authentic accuracy, effectiveness and applicability with government policy.

A proposal for the unified architecture of switches and severs for the efficient processing of multimedia communications and services (멀티미디어 통신과 서비스의 효율적 처리를 위한 교환기-서버 통합구조의 제안)

  • 함진호;최병욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.11
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    • pp.2869-2885
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    • 1996
  • There werer many researches on the switch system for high speed netowrk such as B-ISDN and the server system for the multimedia services respectively. But, in case of simple connection of these two systems, we have to suffer the bottlenck problem of data transmission, and pay the wasteful expenditure because of duplicated architecture of both systems such as interconnecting network at the switch and the server. Therefore, we propse the unified architecture of switehces and servers, which can be used as switches and servers simultaneously. This is based on the hybercube structure. The links are used iterconnection network of switch system, and each node has the subscriber subsystem and the server subsystem. The proposed architecure has the benifits as follows; the easy espansion of capacity due to the scalability,the simple system development and maintenance because of the equivalance of each nodes, the high reliability against the fault of nodes and links due to the existence of the many alternative links between nodes, the easy flow and QoS managment due to the non-blocking data transmission between any two nodes, the flexible adaptation for additional new services owing to simple insertion server board to node. In this paper, we present overal configuration and node component of proposed architecture, and the procesing flow for the various services.

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A Study of Delay Test for Sequential circuit based on Boundary Scan Architecure (순서회로를 위한 경계면 스캔 구조에서의 지연시험 연구)

  • Lee, Chang-Hee;Kim, Jeong-Hwan;Yun, Tae-Jin;Nam, In-Gil;Ahn, Gwang-Seon
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.3
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    • pp.862-872
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    • 1998
  • In this paper, we developed a delay test architecture and test procedure for clocked sequential circuit. In addition, we analyze the problems of conventional and previous method on delay test for clocked sequential circuit in IEEE 1149.1. This paper discusses several problems of Delay test on IEEE 1149.1 for clocked sequential circuit. Previous method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a method called ARCH-S, is based on a clock counting technique to generate continuous clocks for clocked input of CUT. A 4-bit counter is selected for the circuit under test. The simulation results ascertain the aecurate operation and effectiveness of the proposed architecture.

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New Pipeline Architecture for Low Power FIR Filter (저전력 FIR 필터를 위한 새로운 파이프라인 아키텍쳐)

  • Paik, Woo-Hyun;Ki, Hoon-Jae;Yoo, Jang-Sik;Lee, Sang-Won;Kim, Soo-Won
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.1
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    • pp.63-73
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    • 1999
  • This paper presents new pipeline architecure for low power and high speed digital FIR filters. The proposed architecture based on retiming technique achieves enhancement on speed by sharing the input delay stage with multiplication of input data and on power combined with supply voltage scaling down technique. An 8-tap digital FIR filter for PRML disk-drive read channels adopting the proposed pipeline architecture has been designed and fabricated with 0.8${\mu}m$ CMOS double metal process technology. Measured results show that the designed FIR filter operates to 192 MHz in average and dissipates 1.22 mW/MHz at 3.3.V power supply. As a result, the proposed architecture improves speed by about 16% and reduces power dissipation by about 23% when operating at the same throughput.

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Analyzing Landscape Ecological Characteristics of Biotope Types in Rural Eco-Villages - Focusing on Eco-Villages of Chonnam Region Designated by Ministry of Environment - (비오톱유형에 의한 농촌생태마을의 경관생태학적 특성분석 -환경부지정 생태마을 중 전남 일부 지역을 대상으로-)

  • Kim, Keun-Ho;Cho, Tong-Buhm;Kim, Mi-Hyang
    • Journal of the Korean Society of Environmental Restoration Technology
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    • v.9 no.6
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    • pp.63-77
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    • 2006
  • The research aim is to classify biotope types of rural eco-villages designed by ministry of environment and analyze landscape ecological characteristics of them. This information would provide information on eco-villages' potential and specific needs to improve landscape ecological structure of eco-villages. Two eco-villages, designated by ministry of environment, in Yoocheon-ri and Sanduk-ri were selected and the landscape ecological metrics used in this study were Area, Shannon diversity index, Shape index, Distance index. The results are as follows. 1) There were five biotope types in large-scale classification, 13 biotope types m Sanduk-ri and 9 biotope types in Yoocheon-ri in middle-scale classification, 31 biotope types in Sanduk-ri and 24 biotope types in Yoocheon-ri in small-scale classification. 2) In the case of area, artificial biotope types, such as artificial forest, agricultural irrigation canal, wet paddy, dry paddy and residential area, covered more than 80% of total area. However, natural biotope types, such as natural forest, river, reservoir, covered just more than 10% of total area. In details, an orchard (26.69%) was the dominant biotope type, followed by artificial forest (19.10%) in Sanduk-ri and the first most abundant biotope type was artificial forest (49.71%), followed by wet paddy (15.95%) in Yoocheon-ri. 3) The result of Shannon diversity index indicated that Sanduk-ri (2.158) had more heterogeneity landscape, rather than Yoocheon-ri (2.051). 4) In the case of shape index, road (13.09) had more complex and irregular shape than either agricultural irrigation canal (3.35) or artificial forest (2.46) in Sanduk-ri. Road (6.52) was also the most irregular biotope shape, followed by river (5.70) and agricultural irrigation canal (4.78) in Yoocheon-ri. 5) Mean Nearest-neighbour Distance (MND) was smallest in wet paddy and dry paddy biotope types in the two study area, suggesting that these biotope types were concentrated within these study areas. From the result, this research suggested information to protect and improve biotopes of eco-villages in the landscape ecological terms. To achieve this improvement plan, there should be strong support by ministry of environment and local governments.

Implementation of Turbo Decoder Based on Two-step SOVA with a Scaling Factor (비례축소인자를 가진 2단 SOVA를 이용한 터보 복호기의 설계)

  • Kim, Dae-Won;Choi, Jun-Rim
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.11
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    • pp.14-23
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    • 2002
  • Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.