• Title, Summary, Keyword: multiprocessors

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A Task Scheduling Scheme for Bus-Based Symmetric Multiprocessor Systems (버스 기반의 대칭형 다중프로세서 시스템을 위한 태스크 스케줄링 기법)

  • Kang, Oh-Han;Kim, Si-Gwan
    • The KIPS Transactions:PartA
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    • v.9A no.4
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    • pp.511-518
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    • 2002
  • Symmetric Multiprocessors (SMP) has emerged as an important and cost-effective platform for high performance parallel computing. Scheduling of parallel tasks and communications of SMP is important because the choice of a scheduling discipline can have a significant impact on the performance of the system. In this paper, we present a task duplication based scheduling scheme for bus-based SMP. The proposed scheme pre-allocates network communication resources so as to avoid potential communication conflicts. The performance of the proposed scheme has been observed by comparing the schedule length under various number of processors and the communication cost.

S3M2: Scalable Scheduling for Shared Memory Multiprocessors (공유 메모리 다중 프로세서 시스템을 위한 가변 스케줄링)

  • Kang, Oh-Han
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.10
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    • pp.3055-3063
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    • 2000
  • In this paper, a task duplication based heuristic scheduling algorithm is proposed to solve the problem of task scheduling on Shared Memory Multiporcessors (SMM). The proposed algorithm pre-allocates network resources so as to avoid potential communication conlhct, and the algorithm uses heuristies to select duplication tasks so as to recuce of a multiprocessors, and generates scheduling accorting to the available number of processors ina system. The proposed algorithm has been applied to some practical task graphs in the simulation, and the results show that the proposed algorithm achieves considerable performance improvement, in respect of schedule length.

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Theoretical Performance Bounds and Parallelization of a Two-Dimensional Packing Algorithm (이차원 팩킹 알고리즘의 이론적 성능 분석과 병렬화)

  • Hwang, In-Jae;Hong, Dong-Kweon
    • The KIPS Transactions:PartA
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    • v.10A no.1
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    • pp.43-48
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    • 2003
  • Two-dimensional packing algorithm can be used for allocating submeshes in mesh multiprocessor systems. Previously, we developed an efficient packing algorithm called TP heuristic, and showed how the results of the packing could be used for allocating submeshes. In this paper, we present theoretical performance bounds for TP heuristic. We also present a parallel version of the algorithm that consumes reduced time when it is executed by multiple processors in mesh multiprocessors.

Memory Behavior in Scientific vs. Commercial Applications

  • Kim, Taegyoun;Heejung Wang;Lee, Kangwoo
    • Proceedings of the IEEK Conference
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    • pp.421-425
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    • 1999
  • As the market size of multiprocessor systems for commercial applications, parallel systems, especially cache-coherent shared-memory multiprocessors that are conventionally designed for scientific applications need to be tuned in different fashion to achieve the best performance for new application area. In this paper, indepth investigation on the memory behavior which is the primary cause for performance changes were made. We chose representative benchmarks in scientific and commercial application areas. After running execution-driven simulation for bus-based cache-coherent shared-memory multiprocessors, we experienced significant differences and conclude that the systems must be carefully and differently designed to achieve the best performance when they are built for distinct applications.

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Fault Detection of the Control System Based on Multiprocessors (다중 프로세서를 이용한 제어 시스템에서의 자체고장탐지)

  • ;;;;Zeung Nam Bien
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.8
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    • pp.906-915
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    • 1988
  • The reliability enhancement is the critical issue in many computer applications, particulary in process control system. In this paper we describe how to achieve the reliability improvement in control system which is based on multiprocessors. The proposed method is accomplished by using the techniques of fault detection which composed by internal and external fault detections, fault isolation for removing the fault propagation, safety action for driving safe input, and fault diagnosis. This approach is experimented and asopted in boiler backup control system constructed by VMEbus system, CPU boards, graphic system, and other interface boards with UNIX operating system.

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Cache Coherence Protocols in NUMA Multiprocessors (NUMA 다중 프로세서에서의 캐쉬 일관성 프로토콜)

  • Moh, Sang-Man;Hahn, Woo-Jong;Yoon, Suk-Han
    • Electronics and Telecommunications Trends
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    • v.13 no.5
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    • pp.11-22
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    • 1998
  • Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.

Energy-Aware Task Scheduling for Multiprocessors using Dynamic Voltage Scaling and Power Shutdown (멀티프로세서상의 에너지 소모를 고려한 동적 전압 스케일링 및 전력 셧다운을 이용한 태스크 스케줄링)

  • Kim, Hyun-Jin;Hong, Hye-Jeong;Kim, Hong-Sik;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.7
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    • pp.22-28
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    • 2009
  • As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

A Diagnosis Algorithm for Hypercube Multiprocessors using Adaptive Cube Partition Method (적응적 큐브 분할을 이용한 하이퍼큐브 진단 알고리즘)

  • Choi, Moon-Ok;Rhee, Chung-Sei
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.4
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    • pp.431-439
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    • 2000
  • In this paper, we propose a system-level diagnosis algorithm for hypercube muti-processors using adaptive cube partition method. Feng[1] proposed a diagnosis algorithm for hypercube multiprocessors which gives a better performance compared to previous researches[2, 3]. But cube partitions in Feng's algorithm are performed without syndrome analysis. Therfore unnecessery overhead is made during cube partitions. In this paper, we propose an adaptive cube partition method which gives better partition through syndrome analysis and reduces diagnosis cost. We give a simulation result for comparisons. We have found that our algorithm shows better performance compared to Feng's method.

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Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors

  • Dorostkar, Aniseh;Asad, Arghavan;Fathy, Mahmood;Jahed-Motlagh, Mohammad Reza;Mohammadi, Farah
    • ETRI Journal
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    • v.40 no.6
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    • pp.759-773
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    • 2018
  • Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

Page replication mechanism using adjustable DELAY counter in NUMA multiprocessors (NUMA 다중처리기에서 조정가능한 지연 카운터를 이용한 페이집 복사 기법)

  • 이종우;조유곤
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.6
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    • pp.23-33
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    • 1996
  • The exploitation of locality of reference in shared memory NUMA multiprocessors is one of the improtant problems in parallel processing today. In this paper, we propose a revised hardeare reference counter to help operating system to manage locality. In contrast to the previous one, the value of counter can abe adjusted dynamically and periodically to adapt the page replication policy to the various memory reference patterns of processors. We use execution-driven simulation of real applications to evaluate the effectiveness of our adjustable DELAY counter. Our main conclusijon is that by using the adjustable DELAY counter the t normalized average memory access costs and the variance of them become smaller for most applications than the previous one and more robust memory management policies can be provided for the operating systems.

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