• Title, Summary, Keyword: on-chip debugger

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Design of On-Chip Debugging System using GNU debugger (GNU 디버거를 이용한 온칩 디버깅 시스템 설계)

  • Park, Hyung-Bae;Ji, Jeong-Hoon;Xu, Jingzhe;Woo, Gyun;Park, Ju-Sung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.24-38
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    • 2009
  • In this paper, we implement processor debugger based on OCD(On-Chip Debugger). Implemented debugger consist of software debugger that supports a functionality of symbolic debugging, OCD integrated into target processor as a function of debugging, and Interface & Control block which interfaces software debugger and OCD at high speed rates. The debugger supports c/assembly level debugging using software debugger as OCD is integrated into target processor. After OCD block is interfaced with 32bit RISC processor core and then implemented with FPGA, the verification of On-Chip Debugging System is carried out through connecting OCD and Interface & Control block, and SW debugger.

Easily Adaptable On-Chip Debug Architecture for Multicore Processors

  • Xu, Jing-Zhe;Park, Hyeongbae;Jung, Seungpyo;Park, Ju Sung
    • ETRI Journal
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    • v.35 no.2
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    • pp.301-310
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    • 2013
  • Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

On-Chip Debug Architecture for Multicore Processor

  • Park, Hyeong-Bae;Xu, Jing-Zhe;Kim, Kil-Hyun;Park, Ju-Sung
    • ETRI Journal
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    • v.34 no.1
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    • pp.44-54
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    • 2012
  • Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

Design and Verification of Efficient On-Chip Debugger for Core-A (Core-A를 위한 효율적인 On-Chip Debugger 설계 및 검증)

  • Xu, Jingzhe;Park, Hyung-Bae;Jung, Seung-Pyo;Park, Ju-Sung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.50-61
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    • 2010
  • Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

Design of Modified JTAG for Debuggers of RISC Processors (RISC 프로세서의 디버거를 위한 변형된 JTAG 설계)

  • Xu, Jingzhe;Park, Hyung-Bae;Jung, Seung-Pyo;Park, Ju-Sung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.7
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    • pp.65-75
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    • 2011
  • As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

The Development of Reusable SoC Platform based on OpenCores Soft Processor for HW/SW Codesign

  • Bin, Young-Hoon;Ryoo, Kwang-Ki
    • Journal of information and communication convergence engineering
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    • v.6 no.4
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    • pp.376-382
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    • 2008
  • Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

Core-A: A 32-bit Synthesizable Processor Core

  • Kim, Ji-Hoon;Lee, Jong-Yeol;Ki, Ando
    • IEIE Transactions on Smart Processing and Computing
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    • v.4 no.2
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    • pp.83-88
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    • 2015
  • Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

Low-Complexity Deeply Embedded CPU and SoC Implementation (낮은 복잡도의 Deeply Embedded 중앙처리장치 및 시스템온칩 구현)

  • Park, Chester Sungchung;Park, Sungkyung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.3
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    • pp.699-707
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    • 2016
  • This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.