• Title, Summary, Keyword: on-chip power module

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A 77GHz MMIC Transceiver Module for Automotive Forward-Looking Radar Sensor

  • Kang, Dong-Min;Hong, Ju-Yeon;Shim, Jae-Yeob;Yoon, Hyung-Sup;Lee, Kyung-Ho
    • Proceedings of the IEEK Conference
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    • pp.609-610
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    • 2006
  • A 77GHz MMIC transceiver module consisting of a power amplifier, a low noise amplifier, a drive amplifier, a frequency doubler and a down-mixer has been developed for automotive forward-looking radar sensor. The MMIC chip set was fabricated using $0.15{\mu}m$ gate-length InGaAs/InAlAs/GaAs mHEMT process based on 4-inch substrate. The power amplifier demonstrated a measured small signal gain of over 20dB from $76{\sim}77GHz$ with 15.5dBm output power. The chip size is $2mm{\times}2mm$. The low noise amplifier achieved a gain of 20dB in a band between $76{\sim}77\;GHz$ with an output power of 10dBm. The chip size is $2.2mm{\times}2mm$. The driver amplifier exhibited a gain of 23dB over a $76{\sim}77\;GHz$ band with an output power of 13dBm. The chip size is $2.1mm{\times}2mm$. The frequency doubler achieved an output power of -16dBm at 76.5GHz with a conversion gain of -16dB for an input power of 10dBm and a 38.25GHz input frequency. The chip size is $1.2mm{\times}1.2mm$. The down-mixer demonstrated a measured conversion gain of over -9dB. The chip size is $1.3mm{\times}1.9mm$. The transceiver module achieved an output power of 10dBm in a band between $76{\sim}77GHz$ with a receiver P1dB of -28dBm. The module size is $8{\times}9.5{\times}2.4mm^3$. This MMIC transceiver module is suitable for the 77GHz automotive radar systems and related applications in W-band.

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An Development of Leakage Current Sensing Module of the System on Chip Type Under Consideration of Electromagnetic Interface in Power Trunk Line (전력간선에서의 전자파 장애를 고려한 원칩형 누설전류 원격 검출단말기의 개발)

  • Kim, Dong-Wan;Park, Ji-Ho;Park, Sung-Won
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.58 no.4
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    • pp.377-384
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    • 2009
  • In this paper, leakage current sensing module of SoC(System on Chip)type and real time monitoring system under consideration of electromagnetic interface in power trunk line are developed. The first, leakage current sensing module of SoC type under consideration of electromagnetic interface is developed, and the developed sensing module of SoC type is composed of leakage sensing part, power supply part, interface part, communication part, AD(Alternating current to Direct current)convert part and amplification part. And also the electromagnetic compatibility is evaluated by conduction and radiation of EMI(Electromagnetic Interference) for developed sensing module. The developed system can have confidence, stability and do energy saving under mixed electric circumstance of the low voltage communication device and high voltage equipment. The second, the real time remote monitoring system is developed using designed wire and wireless communication module with leakage current sensing module of SoC type. The developed real time remote monitoring system can monitor sensing state, occurrence state of leakage current and alarm for each step etc.. And the device configuration, PCB layout for leakage current sensing module of system on chip type and the experiment configuration in consideration of EMI are presented. Also the measurement results of conduction and radiation for EMI are presented.

Development of a Sensor Chip for Phasor Measurement of Multichannel Single Tone Signals (다채널 단일톤 위상 측정칩 개발)

  • Kim, Byoung-Il;Hong, Keun-Pyo;Hwang, Jin-Yong;Chang, Tae-Gyu
    • Proceedings of the IEEK Conference
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    • pp.497-500
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    • 2005
  • This paper presents a design of a hybrid sensor chip which integrates an A/D converter module and a phase measurement module for measuring power line phase. Recursive sliding DFT based phase measurement module is designed using time shared multiplier which can reduce the size of SoC implementation. A/D converter is based on the sigma delta modulation in order to minimize the implementation space of the analog part and designed to obtain 8-bit resolution. Computer simulations and FPGA implementation are performed to verify hybrid sensor chip design. The hybrid sensor chip for 4-channel power line phase measurement is fabricated by using 0.35 micrometer CMOS process.

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Optimized Design of Low Voltage High Current Ferrite Planar Inductor for 10 MHz On-chip Power Module

  • Bae, Seok;Hong, Yang-Ki;Lee, Jae-Jin;Abo, Gavin;Jalli, Jeevan;Lyle, Andrew;Han, Hong-Mei;Donohoe, Gregory W.
    • Journal of Magnetics
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    • v.13 no.2
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    • pp.37-42
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    • 2008
  • In this paper, design parameters of high Q (> 50), high current inductor for on-chip power module were optimized by 4 Xs 3 Ys DOE (Design of Experiment). Coil spacing, coil thickness, ferrite thickness, and permeability were assigned to Xs, and inductance (L) and Q factor at 10 MHz, and resonance frequency ($f_r$) were determined Ys. Effects of each X on the Ys were demonstrated and explained using known inductor theory. Multiple response optimizations were accomplished by three derived regression equations on the Ys. As a result, L of 125 nH, Q factor of 197.5, and $f_r$ of 316.3 MHz were obtained with coil space of $127\;{\mu}m$, Cu thickness of $67.8\;{\mu}m$, ferrite thickness of $130.3\;{\mu}m$, and permeability 156.5. Loss tan ${\delta}=0$ was assumed for the estimation. Accordingly, Q factor of about 60 is expected at tan ${\delta}=0.02$.

Development of Retinal Prosthesis Module for Fully Implantable Retinal Prosthesis (완전삽입형 인공망막 구현을 위한 인공망막모듈 개발)

  • Lee, Kang-Wook;Kaiho, Yoshiyuki;Fukushima, Takafumi;Tanaka, Tetsu;Koyanagi, Mitsumasa
    • Journal of Biomedical Engineering Research
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    • v.31 no.4
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    • pp.292-301
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    • 2010
  • To restore visual sensation of blind patients, we have proposed a fully implantable retinal prosthesis comprising an three dimensionally (3D) stacked retinal chip for transforming optical signal to electrical signal, a flexible cable with stimulus electrode array for stimulating retina cells, and coupling coils for power transmission. The 3D stacked retinal chip is consisted of several LSI chips such as photodetector, signal processing circuit, and stimulus current generator. They are vertically stacked and electrically connected using 3D integration technology. Our retinal prosthesis has a small size and lightweight with high resolution, therefore it could increase the patients` quality of life (QOL). For realizing the fully implantable retinal prosthesis, we developed a retinal prosthesis module comprising a retinal prosthesis chip and a flexible cable with stimulus electrode array for generating optimal stimulus current. In this study, we used a 2D retinal chip as a prototype retinal prosthesis chip. We fabricated the polymide-based flexible cable of $20{\mu}m$ thickness where 16 channels Pt stimulus electrode array was formed in the cable. Pt electrode has an impedance of $9.9k{\Omega}$ at 400Hz frequency. The retinal prosthesis chip was mounted on the flexible cable by an epoxy and electrically connected by Au wire. The retinal prosthesis chip was cappted by a silicone to pretect from corrosive environments in an eyeball. Then, the fabricated retinal prosthesis module was implanted into an eyeball of a rabbit. We successfully recorded electrically evoked potential (EEP) elicited from the rabbit brain by the current stimulation supplied from the implanted retinal prosthesis module. EEP amplitude was increased linearly with illumination intensity and irradiation time of incident light. The retinal prosthesis chip was well functioned after implanting into the eyeball of the rabbit.

Design by Topology Optimization and Performance Test of Ultrasonic Bonding Module for Flip-Chip Packaging (초음파 플립칩 접합 모듈의 위상최적화 설계 및 성능 실험)

  • Kim, Ji Soo;Kim, Jong Min;Lee, Soo Il
    • Journal of Welding and Joining
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    • v.30 no.6
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    • pp.113-119
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    • 2012
  • Ultrasonic bonding is the novel packaging method for flip-chip with high yield and low-temperature bonding. The bonding module is a core part of the bonding machine, which can transfer the ultrasonic energy into the bonding spot. In this paper, we propose topology optimization technique which can make new design of boding modules due to the constraints on resonance frequency and mode shapes. The designed bonding module using topology optimization was fabricated in order to evaluate the bonding performance and reliable operation during the continuous bonding process. The actual production models based on the proposed design satisfied the target frequency range and ultrasonic power. The bonding test was performed using flip-chip with lead-free Sn-based bumps, the results confirmed that the bonding strength was sufficient with the designed bonding modules. Also the performance degradation of the bonding module was not observed after the 300-hour continuous process with bonding conditions.

Characterization of the Soldering Interface in Power Modules by Peel Strength Measurement (벗김강도 측정법에 의한 파워 모듈의 솔더접합 특성 평가)

  • Kim, Nam-Kyun;Lee, Hee-Heung;Bahng, Wook;Seo, Kil-Soo;Kim, Eun-Dong
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.12
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    • pp.1142-1149
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    • 2003
  • The strength and characteristics of the soldering interface of the power semiconductor chip in a power module has been firstly surveyed by the peel strength measurement method. A power module is combined with several power chips which generally has 30∼400$\textrm{mm}^2$ chip area to allow several tens or bigger amps in current rating, so that the traditional methods for interface characterization like shear test could not be applied to high power module. In this study power diode modules were fabricated by using lead-tin solder with 10${\times}$10$\textrm{mm}^2$ or 7${\times}$7$\textrm{mm}^2$ soldering interface. The peel strengths of soldered interfaces were measured and then the microscopic investigation on the fractured surfaces were followed. The peel test indicated that the crack propagated either through the bulk of the soft lead-tin solder which has 55-60 kgf/cm peel strength or along the interface between the solder and the plated nickel layer which has much lower 22 kgf/cm strength. This study showed that the peel test would be a useful method to quantify the solderability as well as to recognize which is the worst interface or the softest material in a power module with a large soldering area.

Analysis of Power Noises by Chip-to-Chip Power Coupling on High-Speed Memory Modules (고속 메모리 모듈에서 칩 간의 파워커플링에 의한 파워 잠음 분석)

  • 위재경
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.31-39
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    • 2004
  • This paper illustrates the noise characteristics under chip's core operations according to types of packages and modules for DDR DRAM For analyzing this, the impedance profiles and power noises are analyzed with DRAM chips having commercial TSOP package and commercial FBGA package on TSOP-based DIMM and FBGA-based DIMH In controversy with common concepts, we find that the noise-isolation characteristics of FBGA package are more weak and sensitive on transferred noises than those of the TSOP package. In addition, the simulated results show that the decoupling capacitor locations of modules are more important to control the self and transfer noise characteristics than the lead inductance of the packages. Therefore, satisfying the target spec of the noise suppression and isolation can be achieved through the design of power distribution systems only with considering not only the package types but also the whole module system.

Ultra-small Form-Factor Helix on Pad-Type Stage-Bypass WCDMA Tx Power Amplifier Using a Chip-Stacking Technique and a Multilayer Substrate

  • Yoo, Chang-Hyun;Kim, Jung-Hyun
    • ETRI Journal
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    • v.32 no.2
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    • pp.327-329
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    • 2010
  • A fully integrated small form-factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix-on-pad integrated passive device output matching, a chip-stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm ${\times}$ 2.2 mm. A stage-bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.

A Study on the Convective Heat Transfer in Micro Heat Exchanger Embedded in Stacked Multi-Chip Modules (적층형 Multi-Chip Module(MCM) 내부에 삽입된 초소형 열교환기 내에서의 대류 열전달 현상에 대한 연구)

  • Shin, Joong-Han;Kang, Moon-Koo;Lee, Woo-Il
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.28 no.6
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    • pp.774-782
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    • 2004
  • This article presents a numerical and experimental investigation for the single-phase forced laminar convective heat transfer through arrays of micro-channels in micro heat exchangers to be used for cooling power-intensive semiconductor packages, especially the stacked multi-chip modules. In the numerical analysis, a parametric study was carried out for the parameters affecting the efficiency of heat transfer in the flow of coolants through parallel rectangular micro-channels. In the experimental study, the cooling performance of the micro heat exchanger was tested on prototypes of stacked multi-chip modules with difference channel dimensions. The simulation results and the experiment data were acceptably accordant within a wide range of design variations, suggesting the numerical procedure as a useful method for designing the cooling mechanism in stacked multi-chip packages and similar electronic applications.