• Title, Summary, Keyword: phase detector (PD)

Search Result 29, Processing Time 0.051 seconds

Design of low jitter CDR using a single edge binary phase detector (단일 에지 이진위상검출기를 사용한 저 지터 클록 데이터 복원 회로 설계)

  • An, Taek-Joon;Kong, In-Seok;Im, Sang-Soon;Kang, Jin-Ku
    • Journal of IKEEE
    • /
    • v.17 no.4
    • /
    • pp.544-549
    • /
    • 2013
  • This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu $0.13{\mu}m$ CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.

3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling (4X 오버샘플링을 이용한 3.125Gbps급 기준 클록이 없는 클록 데이터 복원 회로)

  • Jang, Hyung-Wook;Kang, Jin-Ku
    • Journal of IKEEE
    • /
    • v.10 no.1
    • /
    • pp.10-15
    • /
    • 2006
  • In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

  • PDF

A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

  • Yoo, Jae-Wook;Kim, Tae-Ho;Kim, Dong-Kyun;Kang, Jin-Ku
    • ETRI Journal
    • /
    • v.33 no.5
    • /
    • pp.752-758
    • /
    • 2011
  • This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

Design of a Clock and Data Recovery Circuit Using the Multi-point Phase Detector (다중점 위상검출기를 이용한 클럭 및 데이터 복원회로 설계)

  • Yoo, Sun-Geon;Kim, Seok-Man;Kim, Doo-Hwan;Cho, Kyoung-Rok
    • The Journal of the Korea Contents Association
    • /
    • v.10 no.2
    • /
    • pp.72-80
    • /
    • 2010
  • The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

Analysis of Insulation Aging in Operating High Voltage Motors (운전중인 고압전동기에서 절연열화 분석)

  • Kim, Hee-Dong;Ju, Young-Ho
    • Proceedings of the KIEE Conference
    • /
    • /
    • pp.2175-2178
    • /
    • 2005
  • During normal machine operation, partial discharge(PD) measurements were performed with turbine generator analyzer(TGA) in five high voltage motors(rated 6.6kV). These high voltage motors were installed with 80pF capacitive couplers at the terminal box. The PD patterns were displayed two dimensional and three dimensional. TGA summarizes each plot with two quantities such as the normalized quantity number(NQN) and the peak PD magnitude(Qm). Off-line PD measurements were conducted on five motors. These motors were energized to 3.81kV. The PD levels in pC were measured with a conventional digital PD detector. The comparison of positive to negative PD indicates whether the defect elements of PD are within the insulation or on the insulation surface. Internal discharges were generated in phase A, B and C of COP-B and pulv.-B, in phase B of Pulv. C and in phase C of Pulv.-D motor. Discharge at conductor surface was discovered in phase A of Pulv. D motor. Slot discharges occurred in three phases of Pulv. E motor.

  • PDF

A Study on a Noise Robust PD/FD for DPLL for Optical Storage (광 저장장치용 DPLL을 위한 Noise Robust PD/FD에 관한 연구)

  • 배주한;박현수;김민철;심재성;서재훈;홍유표;이재진
    • Proceedings of the IEEK Conference
    • /
    • /
    • pp.2180-2183
    • /
    • 2003
  • 본 논문에서는 광 디스크의 기록 밀도 증가에 따른 신호품질의 열화나 노이즈가 심한 환경에서 DPLL(Digital Phase Locked Loop)의 성능을 개선하기 위한 FD(Frequency Detector)와 PD(Phase Detector) 알고리즘을 제안한다. 제안된 PD 알고리즘은 노이즈에 의해 왜곡되어 RLL 조건을 위배하는 입력신호, 즉 RLL 조건에 의해 결정되는 최소 런 길이보다 주기가 작은 신호에 의해 발생하는 위상오차를 위상오차 보정 시 사용하지 않도록 설계하여 잘못된 정보에 의한 위상오차 보정이 일어나지 않도록 하였다 제안된 FD 알고리즘은 주파수를 추적하기 위해 삽입되는 신호인 Sync 신호의 symmetry 특성을 이용하여 샘플패턴을 검출하도록 하여 기존의 주파수 오차 보정 알고리즘보다 향상된 주파수 추적 성능을 가지도록 하였다.

  • PDF

A Four State Rotational Frequency Detector for Fast Frequency Acquisition

  • Yeo, Hyeop-Goo
    • Journal of information and communication convergence engineering
    • /
    • v.9 no.3
    • /
    • pp.305-309
    • /
    • 2011
  • This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

An Analytical Approximation for the Pull-Out Frequency of a PLL Employing a Sinusoidal Phase Detector

  • Huque, Abu-Sayeed;Stensby, John
    • ETRI Journal
    • /
    • v.35 no.2
    • /
    • pp.218-225
    • /
    • 2013
  • The pull-out frequency of a second-order phase lock loop (PLL) is an important parameter that quantifies the loop's ability to stay frequency locked under abrupt changes in the reference input frequency. In most cases, this must be determined numerically or approximated using asymptotic techniques, both of which require special knowledge, skills, and tools. An approximating formula is derived analytically for computing the pull-out frequency for a second-order Type II PLL that employs a sinusoidal characteristic phase detector. The pull-out frequency of such PLLs can be easily approximated to satisfactory accuracy with this formula using a modern scientific calculator.

A 0.12GHz-1.4GHz DLL-based Clock Generator with a Multiplied 4-phase Clock Using a 0.18um CMOS Process

  • Chi, Hyung-Joon;Lee, Jae-Seung;Sim, Jae-Yoon;Park, Hong-June
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.6 no.4
    • /
    • pp.264-269
    • /
    • 2006
  • A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

A 3.2Gb/s Clock and Data Recovery Circuit without Reference Clock for Serial Data Communication (시리얼 데이터 통신을 위한 기준 클록이 없는 3.2Gb/s 클록 데이터 복원회로)

  • Kim, Kang-Jik;Jung, Ki-Sang;Cho, Seong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SC
    • /
    • v.46 no.2
    • /
    • pp.72-77
    • /
    • 2009
  • In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.