대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)

대한전기학회 (The Korean Institute of Electrical Engineers)
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Domino CMOS NOR-NOR Array Logic의 Testable Design에 관한 연구

A study on the Testable Design of Domino CMOS NOR-NOR Array Logic

  • 이중호 (울산대학교 전자 및 전산기 공학과) ;
  • 조상복 (울산대학교 전자 및 전산기 공학과)
  • Lee, Joong-Ho (Dept. of Electronic and Computer Engineering, university of ulsan) ;
  • Cho, Sang-Bock (Dept. of Electronic and Computer Engineering, university of ulsan)
  • 발행 : 1988.07.01
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초록

This paper proposes testable design method of Domino CMOS NOR-NOR Array Logic design method. Previous Domino CMOS PLA method is composed of 2 level NAND-NAND Logic. Because NOR-NOR Logic is realized by a parallel circuit, this method can prevent delay time each level and DNOR-PLA include testable circuit system that DNOR-PLA circuit. DNOR-PLA testable algorithm is realized on Prime (Primos) in Pascal language and DNOR-PLA circuit is simulated by PSPICE.

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