재비교기를 이용한 PLC용 Dataflow LSP구조에 관한 연구

A Study on the Architecture of Dataflow LSP using Re-matching Unit

  • 박재현 (서울대학교 제어계측공학과) ;
  • 장래혁 (서울대학교 제어계측공학과) ;
  • 권욱현 (서울대학교 제어계측공학과)
  • Park, Jae-Hyun (Dept. of Control and Instrumentation Engineering Seoul National University) ;
  • Chang, Nae-Hyuck (Dept. of Control and Instrumentation Engineering Seoul National University) ;
  • Kwon, Wook-Hyun (Dept. of Control and Instrumentation Engineering Seoul National University)
  • 발행 : 1991.07.18

초록

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP(dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. And also, it has dynamic load balancing capabilites which increases the utilization of the whole system that can he hardly implemented in other multiprocessor system. The re-matching unit gets rid of unnecessary matching cycles in LSU, which increases the performance of LSU and allows the multiple input multiple output operations.

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