A Circuit Design for Clamping an Overvoltage in Three-level Inverters

3-레벨 인버터를 위한 과전압 제한회로 설계

  • 정재훈 (한양대학교 전기공학과) ;
  • 이요한 (한양대학교 전기공학과) ;
  • 현동석 (한양대학교 전기공학과)
  • Published : 1995.11.18

Abstract

This paper represents an overvoltage clamping circuit for three level inverters. With a proposed overvoltage clamping circuit, the problems that high voltage stresses and voltage unbalance between outer and inner switches occurs in high power and high voltage 3-level inverters are reduced.

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