다단 Viterbi 부호기를 사용한 가변 에러정정 기법

Selective FEC using Multi-Stage Viterbi Coder

  • 박태근 (명지대학교 전자공학과) ;
  • 이준화 (명지대학교 전자공학과) ;
  • 박재현 (명지대학교 전자공학과) ;
  • 최병석 (명지대학교 전자공학과) ;
  • 박현민 (명지대학교 전자공학과)
  • 발행 : 1998.10.01

초록

In this paper, to reduce BER(Bit Error Rate) in satellite ATM Networks, a new scheme for FEC(Forward Error Corection) using multi-stage Viterbi coder is proposed. In terms of structural complexity, proposed multi-stage Viterbi coder is simpler than the traditional single-stage coder based on the same BER performances. and, through simulation, proposed coder shows excellent error correction capabilities, compared with traditional FEC schemes. Also, we propose a selective FEC mechanism that adaptively changes the number of stages to satisfy the QoS(Quality of Service) requirements. This Selective scheme can be easily implemented using the PLCP(Physical Layer Convergence Protocol) frame structure.

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