선택적 프리차지 방법을 갖는 500MHz 1.1㎱ 32kb SRAM 마크로 설계

A 500MHz 1.1㎱ 32kb SRAM Macro with Selective Bit-line Precharge Scheme

This paper presents a 500MHz 1.1㎱ 32kb synchronous CMOS SRAM macro using $0.35\mu\textrm{m}$ CMOS technology. In order to operate at high frequency and reduce power dissipation, the designed SRAM macro is realized with optimized decoder, multi-point sense amplifier(MPSA), selective precharge scheme and etc. Optimized decorder and MPSA respectively reduce 50% and 40% of delay time. Also, a selective precharge scheme reduces 80% of power dissipation in that part.