상위 수준 설계에서의 테스트패턴 생성

High Level Test Generation

IC testing plays a very important role in IC manufacturing process. Modern complex ASIC chips making it difficult for gate level and RLT level test generation techniques to generate good test vector in resonable time. In this paper we proposed new test pattern generation method in VHDL description to detect manufacturing faults. This method based on software testing can easily generate test vector and independent to synthesis result.