부동소수점 라운딩 병렬화 알고리즘의 하드웨어 구현을 위한 구조 설계

Architectural Design for Hardware Implementations of Parallelized Floating-point Rounding Algorithm

Hardware to implement the parallelized Floating-point rounding algorithm is described. For parallelized additions, we propose an addition module which has carry selection logic to generate two results accoring to the input valuse. A multiplication module for parallelized multiplications is also proposed to generate Sum and Carry bits as intermediate results. Since these modules process data in IEEE standard Floatingpoint double precision format, they are designed for 53-bit significands including hidden bits. Multiplication module is designed with a Booth multiplier and an array multiplier.