대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1998년도 추계종합학술대회 논문집
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- Pages.1153-1156
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- 1998
다중 칩 수퍼스칼라 마이크로프로세서용 부동소수점 연산기의 설계
Design of Floating-point Processing Unit for Multi-chip Superscalar Microprocessor
초록
We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.
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