Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Negative Bias Stress Effect with Offset Structure in Poly-Si TFT's

Offset 구조 Poly-Si TFT의 Negative Bias Stress 효과

  • 이제혁 (수원대학교 전자재료공학과) ;
  • 변문기 (수원대학교 전자재료공학과) ;
  • 임동규 (수원대학교 전자재료공학과) ;
  • 조봉희 (수원대학교 전기전자정보통신 공학부) ;
  • 김영호 (수원대학교 전자재료공학과)
  • Published : 1998.11.01
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Abstract

The electrical characteristics of poly-Si TFT's with offset structure by negative bias stress are systematically investigated as a function of offset length. The changes of electrical characteristics, V$\_$th/, off-current, on/off ratio, in the offset structured poly-Si TFT's are smaller than that of the conventional structured poly-Si TFT's under the stress condition (V$\_$ds/=20V, V$\_$gs/=-20V). It is found that the hot carrier effect by negative bias stress is suppressed by the offset structured poly-Si TFT's because the local electric field near the drain region is decreased by offset region.

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