대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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- Pages.600-602
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- 1998
파이프라인 구조를 갖는 회로를 위한 내장된 자체 검사 설계에 관한 연구
A Study on Design of BIST for Circuits with Pipeline Architecture
- Yang, Sun-Woong (Dept. Computer Science, Soongsil Univ.) ;
- Han, Jae-Cheon (Dept. Computer Science, Soongsil Univ.) ;
- Jin, Myung-Koo (Dept. Computer Science, Soongsil Univ.) ;
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Chang, Hoon
(Dept. Computer Science, Soongsil Univ.)
- 발행 : 1998.11.28
초록
In this paper, we implement BIST to efficiently test circuits with pipeline architecture and JTAG to control implemented BIST and support board level test. Since implemented BIST is designed to be initialized using new seed, hard-to-detect faults are easily detected. Besides, to optimize area overhead, it uses JTAG instead of BIST controller and modified pipeline register instead of added test pattern generator and signature generator. And, to optimize pin overhead, it uses pins of JTAG. Function and efficiency of implemented BIST is verified by simulation.
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