Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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VLSI Design of 3-Bit Soft Decision Viterbi Decoder

3-Bit Soft Decision Viterbi 복호기의 VLSI 설계

  • 김기명 (숭실대학교 정보통신공학과) ;
  • 송인채 (숭실대학교 정보통신공학과)
  • Published : 1999.11.01
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Abstract

In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.

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