AC PDP의 addressing 기간중의 벽전하 분포에 관한 연구

Wall Charge Distribution In the Address Period of AC Plasma Display Panel

The relationships between driving voltage and the wall charge distribution in the address period of surface discharge type AC Plasma Display Panel have been investigated. The quantity of wall charge on each electrode are detected simultaneously from the electrode current after applying only one addressing discharge pulse. The wall charge Qy on the scan electrode Y is nearly the sum of Qx on the address electrode X and Qz on the sustain electrode 2. The Qy increased with the driving voltage regardless of the kind of electrode, whereas the address time Td decreased, Qz and Qy are increased considerably with the blocking voltage Vz, whereas Qx is decreased. The increase rate of Qx, Qy and Qz for increase in Vz was $-13{\times}10^{-2}$(pc/Vz), and $60{\times}10^{-2}$(pc/Vz) and $70{\times}10^{-2}$(pc/Vz), respectively.