Proceedings of the Korea Institute of Convergence Signal Processing (융합신호처리학회 학술대회논문집)

The Korea Institute of Convergence Signal Processing (한국융합신호처리학회)
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Design of the 0-1 Knapsack Processor using VHDL

VHDL을 이용한 0-1 Knapsack 프로세서의 설계

  • 이재진 (충북대학교 컴퓨터공학과) ;
  • 송호정 (충북대학교 컴퓨터공학과) ;
  • 송기용 (충북대학교 컴퓨터공학과)
  • Published : 2000.08.01
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Abstract

The 0-1 knapsack processor performing dynamic programming is designed and implemented on a programmable logic device. Three types of a processor, each with different behavioral models, are presented, and the operation of a processor of each type is verified with an instance of the 0-1 knapsack problem.

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