TMR시스템의 고장안전제어를 위한 FPGA 개발

A FPGA Development for the Fail Safe Control of TMR System

  • 강민수 (광운대학교 제어계측공학과) ;
  • 이정석 (광운대학교 제어계측공학) ;
  • 김현기 (광운대학교 제어계측공학) ;
  • 유광균 (한국철도대학 철도신호) ;
  • 이기서 (광운대학교 제어계측공학과)
  • 발행 : 2000.05.01

초록

This paper proposes the failsafe control logic. which has applied to the voting on the TMR system by using FPGA The self-detection circuit is also designed for detecting a characteristic of fault at TMR system. The fault producing in the self-detection system is largely classified among an intermittent fault, a transient fault and a permanent fault. If it is happened to the permanent fault, the system can be failed. Therefore, it is designed the logic circuit which is not transferred the permanent fault to the system after shut off output. The control logic of the Fail Safe proposed in the paper is required for a circuit integrate of device to minimize the failure happened. Therefore, it makes to design FPGA with modeling of VHDL. The circuit of the Fail Safe of TMR system is able to apply to nuclear system, rail-way system, aerospace and aircraft system which is required for high reliability.

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