Intel486 병렬시스템의 Cache Coherence를 위한 Central Directory Unit의 설계

Design of Central Directory Unit for Cache Coherence of Multiprocessor based on Intel486 Microprocessor

In order to utilize cache in multiprocessor system, cache coherence problem must be handled. Central directory scheme is one of hardware-assisted cache coherence solutions. The goal of this paper was not only to propose some special methods needed to apply central directory scheme to the specific multiprocessor system based on Intel486 microprocessors but also to design central directory unit for cache coherence of the target system. The problems of arbitrating several requests from processors, storing the cache information, and generating control signals for cache line fill and snoop cycle were solved.