Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.07a
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- Pages.98-101
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- 2002
A Low-Power LSI Design of Japanese Word Recognition System
- Yoshizawa, Shingo (Graduate School of Engineering, Hokkaido University) ;
- Miyanaga, Yoshikazu (Graduate School of Engineering, Hokkaido University) ;
- Wada, Naoya (Graduate School of Engineering, Hokkaido University) ;
- Yoshida, Norinobu (Graduate School of Engineering, Hokkaido University)
- Published : 2002.07.01
Abstract
This paper reports a parallel architecture in a HMM based speech recognition system for a low-power LSI design. The proposed architecture calculates output probability of continuous HMM (CHMM) by using concurrent and pipeline processing. They enable to reduce memory access and have high computing efficiency. The novel point is the efficient use of register arrays that reduce memory access considerably compared with any conventional method. The implemented system can achieve a real time response with lower clock in a middle size vocabulary recognition task (100-1000 words) by using this technique.
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