Efficient Block Packing to Minimize Wire Length and Area

In layout of LSI and PWB, block pack- ing problem is very important in order to reduce chip area. Sequence-pair is typical one of conventional pack- ing method and can search nearly-optimal solution by using Simulated Annealing(SA). SA takes huge computation time due to evaluating of various packing results. Therefore, Sequence-pair is not effective enough for fast layout evaluation including estimation of wire length and rotation of every blocks. This paper proposes an efficient block packing method to minimize wire length and chip area. Our method searches an optimal packing efficient- ly by using a cluster growth algorithm with changing the most valuable packing score on packing process.