A Proposal of Programmable Logic Architecture for Reconfigurable Computing

Reconfigurable computing is a new computing paradigm which has more potential in terms of performance and flexibility. Reconfigurable computing systems are opening a new era in digital signal processing such as multimedia, communication and consumer electronics because they can filter data rapidly and excel at pattern recognition, image process- ing and encryption. Although many reconfigurable computing systems use a conventional programmable device, they carry several serious problems to be solved. This paper proposes a logic block architecture of programmable device suit-able for the reconfigurable computing. Compared to conventional logic blocks, our logic block can improve implementation density, efficiency and speed.