An Ultra-High Speed 1.7ns Access 1Mb CMOS SRAM macro

  • T.J. Song (Design Technology Dept., System LSI Div., SamSung Ltd) ;
  • E.K. Lim (Design Technology Dept., System LSI Div., SamSung Ltd) ;
  • J.J. Lim (Design Technology Dept., System LSI Div., SamSung Ltd) ;
  • Lee, Y.K. (Design Technology Dept., System LSI Div., SamSung Ltd) ;
  • Kim, M.G. (Design Technology Dept., System LSI Div., SamSung Ltd)
  • Published : 2002.07.01

Abstract

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

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