Effect of Power Control Step Size on the Performance of the SIC Scheme in Power-Controlled DS/CDMA Systems

  • Lee, Chiho (Department of Information and Communications, Kwang-Ju Institute of Science and Technology (K-JIST)) ;
  • Kim, Kiseon (Department of Information and Communications, Kwang-Ju Institute of Science and Technology (K-JIST))
  • Published : 2002.07.01

Abstract

In this paper, we investigate the effect of power control step size on the performance of the SIC scheme in DS/CDMA systems. We investigate the average power control iteration and its standard deviation and evaluate the outage performance for several different values of power control step size. Because the SIC scheme requires fine control in the received signal power, the better outage performance is obtained fer the smaller power control step size. However, the smaller power control step size requires larger amount of power control iteration in order to make the power control converge to the steady state. Under the simulated environment, the proper power control step size is about 0.3-0.4dB from both convergence speed of power control algorithm and outage performance points of view.

Keywords