Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.07c
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- Pages.1968-1971
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- 2002
A Hierarchical Test Generation for Asynchronous Circuits
- Eunjung Oh (Dept. of Info. & Comm., K-JIST) ;
- Kim, Soo-Hyun (Dept. of Info. & Comm., K-JIST) ;
- Lee, Dong-Ik (Dept. of Info. & Comm., K-JIST) ;
- Park, Ho-Yong (School of ECE, Chungbuk Nat’l. Univ.)
- Published : 2002.07.01
Abstract
In this paper, we have presented a test- ing method for a kind of asynchronous circuits. Tar- get circuit model is the 3D machine that is one of the most successful implementation of extended burst-mode (XBM) machines. We present a high-level test generation method for the 3D machine using the specification of the circuit. We also present a gate-level test pattern generation method using a synchronous test pattern generator. Experimental results show that the combination of the above two methods achieves high fault coverage over 3D machines and saves test generation time.
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