0.25 D/R Logic Process를 적용한 $0.05um^2$급 MTJ Cell Integration

  • I. W. Jang (Memory Research & Development Division, Hynix Semiconductor Inc.) ;
  • Lee, K. N. (Memory Research & Development Division, Hynix Semiconductor Inc.) ;
  • S. K. Hong (Memory Research & Development Division, Hynix Semiconductor Inc.) ;
  • Park, Y. J. (Memory Research & Development Division, Hynix Semiconductor Inc.)
  • Published : 2003.06.01