Design of Serial ATA Transport layer

직렬 ATA 전송층 설계

In this Paper, we report a design of Serial ATA Transpor layer. The functionalities of the Serial ATA transport layer are first described on RTL via verilog. The compiled code are then fed to a synthesizer synopsys to get the actual hardware from 0.35$\mu\textrm{m}$ SAMSUNG standard cell library. The designed functionalities of this chip will be verified using test bold with FPGA equipment and ATS2 digital test equipment.